Circuit and method for testing a ferroelectric memory device
AssigneeSTMicroelectronics S.r.l.
InventorDavid C. McClure
Life of this patent
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Abstract
A test circuit and method are disclosed for testing memory cells of a ferroelectric memory device having an array of ferroelectric memory cells. The test circuitry is coupled to the bit lines, for selectively determining the voltage levels appearing on the bit lines based on a measured current level and providing externally to the ferroelectric memory device an electrical signal representative of the sensed voltage levels. In this way, ferroelectric memory cells exhibiting degraded performance may be identified.
Claims39
A random access memory device in an integrated circuit chip, comprising:
- a memory array of memory cells organized into rows and columns, including a plurality of word lines and bit lines, each row of memory cells being coupled to a word line and each column of memory cells being coupled to a bit line;
- sense amplifier circuitry coupled to the bit lines and being selectively disabled;
- address decode circuitry for receiving an address value and asserting a row line associated therewith;
- and
- test circuitry, coupled to at least one bit line, for placing on an external pad of the integrated circuit chip a current level corresponding to a voltage level appearing on the at least one bit line, while concurrently disabling the sense amplifier circuitry.
A method of testing a semiconductor memory device having an array of memory cells and sense amplifier circuitry coupled to bit lines of the array, the semiconductor memory device being in an integrated circuit chip, the method comprising:
- connecting memory cells in a row of memory cells to bit lines of the array;
- disabling the sense amplifier circuitry from driving the bit lines;
- selecting a bit line;
- and
- providing a current level to a pad in the integrated circuit chip corresponding to a voltage level appearing on the selected bit line.
An apparatus, comprising:
- a random access memory device, comprising:
- a memory array of memory cells organized into rows and columns, including a plurality of word lines and bit lines, each row of memory cells being coupled to a word line and each column of memory cells being coupled to a bit line;
- address decode circuitry for receiving an address value and asserting a row line associated therewith;
- and
- test circuitry, coupled to at least one bit line for placing on an external pad a current level corresponding to a voltage level appearing on the at least one bit line.
An apparatus, comprising:
- a ferroelectric capacitor;
- and
- means for placing on an external pad of the apparatus a current level corresponding to a voltage level appearing across the ferroelectric capacitor.
Dependencies are inferred from the claim text.