Method for operating a non-volatile memory

A method for operating a non-volatile memory device, which is applicable for operating an array of memory cells, and the array of the memory cells comprises a plurality of the memory cells, a plurality of word lines, a plurality of bit lines, a plurality of source lines and a plurality of well lines, wherein the memory cells are arranged in rows and columns, a drain region of each memory cell in each column is coupled to a corresponding one of the bit lines, a source region of each memory cell in each column is coupled to a corresponding one of the source lines, a control gate of each memory cell in each row is coupled to a corresponding one of the word lines, a well region of each memory cell in each column is coupled to a corresponding one of the well lines, the method comprising:

• applying a first positive voltage to one of the word lines that is coupled to a selected one of the memory cells, applying a first negative voltage to one of the bit lines that is coupled to the selected memory cell, applying a second negative voltage to the well line that is coupled to the selected memory cell, setting the source line that is coupled to the selected memory cell at floating, grounding the bit lines of a plurality of non-selected memory cells that are commonly connected to the word line of the selected memory cell, setting the well lines of the plurality of the non-selected memory cells that are commonly connected to the word line of the selected memory cell floating to program the selected memory cell and to inhibit programming of the non-selected memory cells;
• and
• applying a third negative voltage to the one of the word lines that is coupled to the selected memory cell, applying a second positive voltage to the one of the bit lines that is coupled to the selected memory cell, applying a third positive voltage to the the well line that is coupled to the selected memory cell,, setting the source line that is connected to the selected memory cell floating, setting the well lines of the plurality of the non-selected memory cells that are commonly connected to the word line of the selected memory cell floating and concurrently grounding the bit lines that are coupled to the plurality of the non-selected memory cells that commonly share the word line with the selected memory cell to erase the selected memory cell and to inhibit erasing of the non-selected memory cells.