System for programming verification
AssigneeFujitsu Limited
InventorMasaru Yano
Life of this patent
Estimating the term…
Abstract
System for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device. The system operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.
Claims8
A method for performing program verification of memory cells in a NAND memory device to achieve selected Vt levels, the NAND memory device includes page buffers having disable gates that operate to enable or disable programming of selected memory cells, the method comprising steps of:
- (a) performing a programming cycle to program the memory cells to have the selected Vt levels;
- (b) setting a first verification level;
- (c) verifying that the memory cells have the selected Vt levels using the first verification level, wherein passed and failed memory cells are determined;
- (d) inhibiting, using the disable gates, the passed memory cells from further programming;
- (e) setting a second verification level;
- (f) verifying that the failed memory cells have a second selected Vt level using the second verification level, wherein second passed and second failed memory cells are determined;
- (g) adjusting a programming pulse to have a first strength level when the second passed memory cells are determined;
- (h) adjusting the programming pulse to have a second strength level when the second failed memory cells are determined;
- (i) re-programming the failed memory cells with the programming pulse;
- and
- (j) repeating steps (b) through (i) above until the memory cells have the selected Vt levels.
Apparatus for performing program verification in a NAND memory device, the apparatus comprising:
- a page buffer coupled to a bit line, the page buffer including a latch coupled to a data input, the latch producing an inhibit signal;
- and
- a programming disable gate coupled between the bit line and a grounding gate, the programming disable gate is further coupled to receive the inhibit signal, wherein when the inhibit signal is in a first state the programming gate couples the bit line to the grounding gate, and wherein when the inhibit signal is in a second state the programming gate decouples the bit line and the grounding gate.
Dependencies are inferred from the claim text.