Single poly embedded eprom
AssigneeeMemory Technology Inc.
InventorsChing-Sung Yang, Shih-Jye Shen, Ching-Hsiang Hsu
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Abstract
The present invention proposes a novel structure of nonvolatile memory. The aspect of the present invention includes two serially connected PMOS transistor. The characteristic of the devices is that bias is not necessary to apply to the floating gate during the programming mode. Thus, the control gate is omitted for the structure or layout, thereby saving the space for making the control gate. The present invention may “automatically inject” carrier into floating gate for programming the status of the device.
Claims17
An erasable programmable read only memory comprising:
- two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type metal-oxide semiconductor transistor acts as select transistor, a gate of said first P-type metal-oxide semiconductor transistor is coupled to select gate voltage, a first node of said first P-type metal-oxide semiconductor transistor connected to source line voltage, a second node of said first P-type metal-oxide semiconductor transistor connected to a first node of a second P-type metal-oxide semiconductor transistor, wherein a second node of said second P-type metal-oxide semiconductor transistor is connected to bit line voltage, wherein a gate of said second P-type metal-oxide semiconductor transistor serves as a floating gate, wherein said erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto said floating gate.
An erasable programmable read only memory that omits a control gate comprising:
- a doped region formed by ion implantation in a substrate;
- a first conductive area covered on said substrate and forms a first cross structure with a first overlap area to acts as a select transistor gate and connected to a select gate voltage (VSG);
- a second conductive region located at a side of said first conductive region and on said substrate and forms a second cross structure with a second overlap area to acts as a floating gate;
- wherein a feature of said erasable programmable read only memory is that a control gate is omitted, thereby reducing device size and integratable with CMOS process.
An erasable programmable read only memory comprising:
- two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type metal-oxide semiconductor transistor acts as select transistor, a second P-type metal-oxide semiconductor transistor connected to said first P-type metal-oxide semiconductor transistor, wherein a gate of said second P-type metal-oxide semiconductor transistor serves as a floating gate, in a programming mode, a drain of said second P-type metal-oxide semiconductor transistor is biased to a first negative voltage and providing a second negative voltage on said floating gate to perform programming without apply a certain bias on a control gate.
Dependencies are inferred from the claim text.