Cache memory
AssigneeSTMicroelectronics S.r.l.
InventorWilliam Bryan Barnes
Life of this patent
Estimating the term…
Abstract
An integrated cache memory circuit is provided comprising a tag RAM, a comparator and a data RAM. Each of the tag RAM and the date RAM have an array of memory cells and plural sense amplifiers. Each memory cell of the RAMs is connected via a respective bit line to one of the plural sense amplifiers. The sense amplifiers of the tag RAM have respective outputs coupled to a first input of the comparator. The comparator having a second input for address information and an output for selectively enabling data output from sense amplifiers of the data RAM. The memory cells of the tag RAM are arranged to have a higher current drive than the memory cells of the data RAM.
Claims5
An integrated cache memory circuit comprising a tag RAM, a comparator and a data RAM, each of said tag RAM and said data RAM having an array of memory cells and plural sense amplifiers, each memory cell of said RAMs being connectable via a respective bitline to one of said plural sense amplifiers, said sense amplifiers of said tag RAM having respective outputs coupled to a first input of said comparator, said comparator having a second input for address information, and an output for selectively enabling data output from sense amplifiers of said data RAM, wherein the memory cells of said tag RAM are arranged to have a higher current drive than the memory cells of said data RAM.
The memory circuit of any preceding claim wherein said data RAM and tag RAMs share common wordlines.
Dependencies are inferred from the claim text.