Method of writing a four-transistor memory cell array
AssigneeHewlett-Packard Development Company, L.P.
InventorRobert J. Brooks
Life of this patent
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Abstract
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
Claims27
A method of writing a memory array, comprising:
- creating a first voltage differential between a first row-supply line and a second row-supply line;
- and, creating a second voltage differential between a first column-supply line and a second column-supply line.
A method of writing a memory array, comprising:
- driving a first voltage differential between a first supply line and a second supply line wherein said first supply line is connected to a first inverter in a plurality cells of a row and said second supply line is connected to a second inverter in a plurality of cells of said row thereby causing a first current to flow between said first supply line and at least a third supply line when a cell of said plurality of cells in said row is in a first state;
- and,
- driving a second voltage differential between said third supply line and a fourth supply line thereby causing said cell to switch between said first state and a second state and wherein said third supply line is connected to said first inverter and said fourth supply is connected to said second inverter.
A method of writing a memory array, comprising:
- creating a first voltage differential between a first column-supply line and a second column-supply line;
- and,
- creating a second voltage differential between a first row-supply line and a second row-supply line.
A method of writing a memory array, comprising:
- driving a first voltage differential between a first supply line and a second supply line wherein said first supply line is connected to a first inverter in a plurality cells of a column and said second supply line is connected to a second inverter in a plurality of cells of said column thereby causing a first current to flow between said first supply line and at least a third supply line when a cell of said plurality of cells in said column is in a first state;
- and,
- driving a second voltage differential between said third supply line and a fourth supply line thereby causing said cell to switch between said first state and a second state and wherein said third supply line is connected to said first inverter and said fourth supply is connected to said second inverter.
A method of writing a memory array, comprising:
- A method of reading a memory array, comprising:
- supplying a first supply line and a second supply line with a first operating voltage;
- supplying a third supply line and a fourth supply line with a second operating voltage;
- supplying a first voltage differential between said first supply line and said second supply line that is at least a threshold voltage of a first type of field-effect transistor in magnitude thereby causing at least one cell to conduct a detectable amount of current between said first supply line and said third supply line;
- and,
- supplying a second voltage differential between said third supply line and said fourth supply line that is less than a threshold voltage of a second type of field-effect transistor in magnitude thereby causing at least on cell to change from a first logic state to a second logic state.
Dependencies are inferred from the claim text.