Four-transistor static memory cell array
AssigneeHewlett-Packard Development Company, L.P.
InventorRobert J. Brooks
Life of this patent
Estimating the term…
Abstract
A pair of cross-coupled inverters that hold a digital state are powered by supplies that also function as row select and column bit lines. A method of reading and writing the digital state of an individual cell, row of cells, or column of cells by manipulating these row-supply or column-supply lines. Reads and writes may be performed on either a row or column basis. A method for reading and logically OR'ing or AND'ing an entire row or column of cells. A method for querying on a row or column basis to function as a content addressable memory (CAM).
Claims12
A static memory cell array, comprising:
- a plurality of cells comprising a first inverter cross-coupled to a second inverter connected in at least a first row by a first supply line connected to said first inverters and a second supply line connected to said second inverters and at least a first column connected in at least a first column by a third supply line connected to said first inverters and a fourth supply line connected to said second inverters.
An array of static memory cells, comprising:
- two row-supply lines per row of cells, wherein said cells consist of a pair of cross-coupled inverters and each of said two row-supply lines supplies a separate one of said pair of cross-coupled inverters;
- and,
- two column supply-lines per column of cells, wherein each of said two column-supply lines supplies a separate one of said cross-coupled inverters.
A memory array, comprising:
- memory cells consisting of a first inverter having a first output, a first input, a first positive supply node, and a first negative supply node and a second inverter having a second output, a second input, a second positive supply node, and a second negative supply node wherein said first output is connected to said second input and said second output is connected to said first input;
- and wherein said cells are connected in rows by said first positive supply node and said second positive supply node;
- and wherein said cells are connected in columns by said first negative supply node and said second negative supply node.
A memory array, comprising:
- memory cells consisting of a first inverter having a first output, a first input, a first positive supply node, and a first negative supply node and a second inverter having a second output, a second input, a second positive supply node, and a second negative supply node wherein said first output is connected to said second input and said second output is connected to said first input;
- and wherein said cells are connected in columns by said first positive supply node and said second positive supply node;
- and wherein said cells are connected in rows by said first negative supply node and said second negative supply node.
An array of four-transistor memory cells, comprising:
- cells consisting of a first inverter comprised of a first two transistors and a second inverter comprised of a second two transistors wherein said are arranged in rows and columns;
- and wherein said cells in each of said rows are connected to each other by a first supply line and second supply line and said first supply line and said second supply line for each of said rows are not connected to each other and not connected to any first supply lines of another row and not connected to any second supply lines of another row;
- and wherein said cells in each of said columns are connected to each other by a third supply line and fourth supply line and said third supply line and said fourth supply line for each of said columns are not connected to each other and not connected to any third supply lines of another column and not connected to any fourth supply lines of another column.
Dependencies are inferred from the claim text.