Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorDaisaburo Takashima
Life of this patent
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Abstract
In a semiconductor memory device comprising a cell array of memory cells each including a cell transistor and a capacitor, word lines and bit line pairs, the control circuit controls the memory circuit to set the bit lines to a high level to write “1” data into the memory cells regardless of a logic level of data to be written, in a state where a potential of a gate of the cell transistor of each memory cell is raised from a first potential of a standby time to a second potential of an active time, and thereafter to set the bit lines to a low level to write “0” data into the memory cells with “0” data to be written, in a state where the potential of the gate of the cell transistor is changed to a third potential higher than the first potential and lower than the second potential.
Claims2
A semiconductor memory device comprising:
- a semiconductor memory circuit which includes a memory cell array including a plurality of memory cells arranged in a matrix form each constituted of a cell transistor and a ferroelectric capacitor having a first end connected to a source of the cell transistor, a plurality of word lines connected to gates of the cell transistors of the memory cells, a plurality of pairs of bit lines connected to drains of the cell transistors of the memory cells, a plate line connected to a second end of the ferroelectric capacitor, and a plurality of sense amplifier circuits each connected to a corresponding pair of bit lines;
- and
- a control circuit which controls the semiconductor memory circuit in an operation time to raise the word lines to be selected from a first potential to a second potential to read cell data from the memory cells onto the bit lines, thereafter set the bit lines to a high level to write “1” data into the memory cells regardless of a logic level of data to be written, thereafter set the selected word lines to a third potential lower than the second potential and higher than the first potential, set the bit lines to a low level with “0” data to be written to write “0” data into the memory cells, and thereafter to lower the selected word lines to the first potential.
Dependencies are inferred from the claim text.