Nonvolatile ferroelectric memory device and method for driving the same

A method for driving a nonvolatile ferroelectric memory device, in which an active period and a precharge period are repeated, comprising steps of:

• accessing particular cells by a write enable signal in the active period;
• writing “high” data in every cell simultaneously in the active period;
• and
• writing external data in the accessed cells and restoring the rest cells in the active period.

A method for driving a nonvolatile ferroelectric memory device, in which an active period and a precharge period are repeated, comprising steps of:

• reading data being stored in cells and delivering the data to a sense amplifier in the active period;
• writing “high” data in every cell in the active period;
• and
• restoring “low” data in cells which used to have the “low” data before among the cells of which data were read in the first step.

A method for driving a nonvolatile ferroelectric memory device, comprising:

• a NAND gate logically calculating a plurality of X-address signals;
• a NOR gate logically calculating an output signal of the NAND gate and a first wordline control signal;
• a first NMOS transistor having a source being provided with an output signal of the NOR gate, a gate being provided with a second wordline control signal, and a drain acting as an output terminal;
• a second NMOS transistor having a gate being connected to the drain of the first NMOS transistor, a source being provided with a third wordline control signal, and a drain being connected to wordline;
• and
• a third NMOS transistor having a source being connected to the wordline along with the second NMOS transistor, a gate being provided with an output signal of the NAND gate, and a drain being connected to a ground terminal, wherein the wordline is controlled by the first wordline control signal.