Apparatus and method for driving ferroelectric memory

An apparatus for driving a ferroelectric memory in a driving circuit that generates an operation pulse for controlling operation of a ferroelectric chip, the apparatus comprising:

• an address transition detection summation (ATDSUM) value outputting block for generating an address transition detection pulse (ATD) signal by detecting change of an address signal, and for outputting summation of address transition pulses (ATDSUM) generated by a plurality of addresses;
• a pulse width extension/control pulse generating block for extending a pulse width of the summation of the address transition pulses (ATDSUM) and outputting a ship control pulse by using an extended signal;
• a cell operation pulse generating block for generating a cell operating pulse with a pulse width required on a read/write chip operation by using the chip control pulse;
• a write transition detecting block for receiving a buffered /write enable signal and a cell operation pulse and for outputting a write transition detection signal only in an active region of the cell operation pulse;
• a write control pulse generating block for outputting a write control pulse (WCP) according to the write transition detection signal;
• and
• a write operation pulse generating block for outputting a write operation pulse (WOP) to intercept other operation and perform only a write operation in a low level region in accordance with the write control pulse WCP.

A method for driving a ferroelectric memory in a case that one cycle time is divided into intervals of t0, t1, t2, t3, t4, and t5 in order to generate an operation pulse for controlling an operation of a ferroelectric chip, the method comprising the steps of:

• a) generating an address transition detecting pulse (ATD) signal at a starting portion of the t1 period when an address transition is occurred at an end portion of the t0 period;
• b) summing the address transition detection pulse (ATD) pulse and outputting the summed address transition detection pulse (ATDSUM);
• and
• c) extending a pulse width of the summed address transition detection pulse (ATDSUM) so as for an end edge time thereof to extend to the t3 period and producing a control pulse (CP) by using the same;
• wherein a cell operation pulse (OP) from the t2 period to the t5 period according to the control pulse (CP) is produced so that a normal read/write operations is performed from the t2 period to t5 period, and generation of the address transition detection pulse (ATD) signal is intercepted even if a new address is entered into an active period of the cell operation pulse (OP).

A method for driving a ferroelectric memory in a case that one cycle time is divided into intervals of t0, t1, t2, t3, t4, and t5 in order to generate an operation pulse for controlling an operation of a ferroelectric chip, when a /WE signal is transited to a low level in a period where a cell operation pulse (OP), which is outputted by using an address transition detecting pulse (ATD) signal at an ending portion of the t0 period under without change of address, is in a high level, the method comprising the steps of:

• a) transiting a write transition detection pulse to a high level at the t1 period and maintaining the transited write transition detection pulse for the t1 period;
• b) maintaining the write control pulse (WCP) at the high level until an ending time of the t2 period by transiting the write control pulse (WCP) to the high level at a starting time of the t1 period by using the write transition detection pulse;
• and
• c) generating a write operation pulse (WOP) having a low level from an ending time of the t1 period that the write transition detection pulse is transited to the low level to an ending time of the t5 period that the /WE signal is transited to the high level again.