Method to reduce bus voltage stress in a single-stage single switch power factor correction circuit
AssigneeTexas Instruments Incorporated
InventorsJames P. Noon, Alexander Borisovich Uan-Zo-Li
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AssigneeTexas Instruments Incorporated
InventorsJames P. Noon, Alexander Borisovich Uan-Zo-Li
Estimating the term…
The present invention provides an apparatus and method for reducing the voltage stress in a single-stage single-switch (SSSS) converter by modulating the predetermined operating frequency of the converter lower responsive to increasing voltage stress. A control circuit (116) and associated cooperable frequency setting capacitance (CT) and resistance (RT) are coupled to the primary circuit (112) and the secondary circuit (114) of the SSSS converter via a switch (120). A frequency foldback device (180) is coupled to CT or RT and cooperable therewith to lower bus voltage stress by modulating the switch frequency. The operating frequency is modulated (i.e. reduced) from the predetermined operating frequency upon detection of a voltage threshold transition.
An apparatus for providing operating frequency modulation of the switch in a single-stage single-switch converter for reducing voltage stress, comprising:
A method for reducing voltage stress in a single-stage single-switch (SSSS) converter, wherein the switch controller includes a capacitor and a resistor cooperable to set an operating frequency for the switch in which said resistor determines the charging current applied to said capacitor, said method comprising:
Dependencies are inferred from the claim text.