Parallel read with source-clear operation

A method comprising:

• (a) receiving a read clear request comprising a source address which selects a random access memory (RAM) block in a RAM storage;
• (b) transferring data contents of the RAM block to a level-two cache;
• (c) transferring said data contents from the level-two cache to a first block of a level-one cache;
• (d) transferring said data contents from the first block of the level-one cache to an output buffer,
• (e) setting one or more bits in a first dirty tag associated with the first block;
• (f) setting a first mode indicator associated with the first dirty tag to a read clear mode;
• (g) transferring one or more data items from a color fill block in the level-one cache to the level-two cache in response to detecting that said one or more bits of the first dirty tag are set and that the first mode indicator is set to the read clear mode;
• wherein said data contents from the first level-one cache block are usable to generate a displayable image.

A memory interface for controlling accesses to a memory device, wherein the memory device includes a level-one cache, a level-two cache and a storage cell array, the memory interface comprising:

• a memory control processor configured to control fetch operations from the storage cell array to the level-two cache and from the level-two cache to the level-one cache, and to control write back operations from the level-one cache to the level-two cache;
• a data request processor configured to write data items to the level one cache in response to write requests, to control read accesses from the level one cache in response to read requests, wherein the data request processor is further configured to set one or more bits of a first dirty tag to a first state and to set a mode indicator associated with said first dirty tag to a read clear state in response to receiving a read request with an associated read clear indicator;
• a block cleansing unit configured to scan through an array of dirty tags including said first dirty tag, to command a color fill transfer operation from a color fill block of the level-one cache to the level-two cache in response to detecting that said one or bits of the first dirty tag are set to the first state and that the mode indicator is set to the read clear state;
• wherein the memory control processor is configured to transfer one or more data items from the color fill block to the level-two cache in response to said command, wherein the one or more data items correspond to said one or bits of the first dirty tag which are set to the first state.

A memory system comprising:

• a write bus coupling a level one cache of a memory device and a level two cache of the memory device;
• a read bus coupling the level one cache and the level two cache;
• memory control processor configured to control the transfer of source data from source blocks in the level two cache to corresponding allocated blocks in the level one cache;
• a block cleansing unit configured to initiate the transfer of data from a color fill block in the level one cache to each of the source blocks in the level two cache in response to detecting that (a) one or more bits of dirty tags associated with the corresponding allocated block is set to a first state and (b) a mode indicator associated with the allocated block is set to a read clear state;
• wherein the write bus is configured to convey the color fill data from the level one cache to the source blocks in the level two cache in parallel with the read bus conveying said source data from the source blocks in the level two cache to the level one cache.

A memory system comprising:

• a write bus coupling between a level one cache of a memory device and a level two cache of the memory device;
• a read bus coupling between the level one cache and the level two cache;
• memory control processor configured to control the transfer of source data from a first source block in the level two cache to a first allocated block in the level one cache;
• a block cleansing unit configured to initiate the transfer of data from a color fill block in the level one cache to a second source block in the level two cache in response to detecting that (a) one or more bits of a tag associated with a second allocated block in the level one cache is set to a first state and (b) a mode indicator associated with the second allocated block is set to a read clear state;
• wherein the write bus is configured to convey the color fill data from the level one cache to the second source block in the level two cache in parallel with the read bus conveying said source data from the first source block in the level two cache to the level one cache.

A method comprising:

• (a) receiving read requests addressing a random access memory;
• (b) transferring a page of the random access memory to a level two cache;
• (c) transferring blocks of the level two cache to a level one cache;
• (d) transferreing blocks of the level one cache to an output buffer;
• (e) transferring data from blocks in the level one cache to the level two cache;
• wherein (c) and (e) are performed in parallel;
• wherein (e) includes transferring color data from a color fill block in the level one cache to a selected block in the level two cache.