High-speed latch with integrated gate

A latch comprising:

• a first differential amplifier comprising first, second, and third transistors, wherein the first and second transistors couple in parallel and form a particular logic function, and wherein the first and third transistors have sources that couple together, gates that respectively form non-inverting and inverting latch inputs, and drains that respectively form inverting and non-inverting latch outputs;
• a second differential amplifier comprising fourth and fifth transistors having sources that couple together, gates that respectively couple to the inverting and non-inverting latch outputs, and drains that respectively couple to the non-inverting and inverting latch outputs;
• and
• a third differential amplifier comprising sixth and seventh transistors having sources that couple together, wherein the sixth transistor includes a gate that couples to the non-inverting latch output and a drain that couples to the gate of the third transistor.

A method for latching a plurality of input signals received via a plurality of inputs, the method comprising:

• receiving the plurality of input signals at the plurality of inputs;
• forming an initial value for an output based on values of the plurality of input signals;
• sensing the initial value at the output;
• forming a feedback value based on the sensed value;
• and
• driving the output to a final value based at least in part on the feedback value.