Flip flop with reduced leakage current

A flip flop, comprising:

• a master stage comprising a first plurality of transistors, wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain;
• a slave stage comprising a second plurality of transistors, wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain;
• and
• wherein in a low power mode the flip flop is operable to receive a first voltage coupled to the selective conductive path for each of the first plurality of transistors;
• wherein in the low power mode the flip flop is operable to receive a second voltage coupled to the selective conductive path for each of the second plurality of transistors;
• wherein the second voltage is greater than the first voltage and exceeds a threshold voltage for each of the second plurality of transistors;
• wherein in an active mode the master stage is operable to store a digital state at a master output node in response to a first clock transition;
• wherein in the active mode the slave stage is operable to store a digital state at a slave output node in response to a second clock transition;
• and further comprising a multiplexer having a first input coupled to the master output node and a second input coupled to the slave output node;
• wherein the multiplexer is operable to output the digital state stored at the master output node in response to the first clock transition;
• and
• wherein the multiplexer is operable to output the digital state stored at the slave output node in response to the second clock transition.

A method of operating flip flop, the flip flop comprising a master stage comprising a first plurality of transistors, wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain and the flip flop further comprising a slave stage comprising a second plurality of transistors, wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain, the method comprising the steps of:

• in a low power mode of the flip flop, coupling a first voltage coupled to the selective conductive path for each of the first plurality of transistors;
• and
• in the low power mode of the flip flop, coupling a second voltage coupled to the selective conductive path for each of the second plurality of transistors;
• and
• wherein the second voltage is greater than the first voltage.