Clock ratio dsta synchronizer

#The present invention is generally related to integrated circuits (ICs) and, more particularly, to a clock ratio data synchronizer for synchronizing data in one frequency domain to another frequency domain.

#Clock ratio data synchronizers are known and are used to synchronize data moving from one clock frequency domain to another clock frequency domain. For example, clock ratio data synchronizers are known that synchronize data moving from a higher clock frequency domain to a lower clock frequency domain, and vice versa. Currently clock ratio data synchronizers do not provide maximum tolerance between the skews of the clocks of the different clock frequency domains. Maximization of skew tolerance allows for more variation in the clock paths. For example, in cases where both clocks are being generated off-chip, variation between the off-chip clock paths will exist in addition to variation between the on-chip clock paths. As clock frequency increases, the skew tolerance margin (i.e., the maximum allowable difference between the skews) decreases.

#With synchronizers used in non-state-of-the-art ICs, the skew tolerance margins are greater because the clocks run at lower frequencies than in state-of-the-art ICs. Consequently, skew tolerance margins were not a big concern. However, with the ever-increasing demand to increase clock frequencies and data rates, current skew tolerance margins are insufficient using previous clock ratio data synchronizers.

#FIG. 1 is a block diagram of a first example embodiment of an N-to-N−1 clock ratio data synchronizer in accordance with the present invention.

#FIG. 2 is a set of waveforms drawn to facilitate the understanding of the example embodiment shown in FIG. 1.

#FIG. 3 is a block diagram of a second example embodiment of an N−1-to-N clock ratio data synchronizer in accordance with the present invention.

#FIG. 1 is a block diagram of a first example embodiment of an N-to-N−1 clock ratio data synchronizer 1 in accordance with the present invention. The data is input to the synchronizer 1 at input terminal 2 and is sampled by the higher clock domain, N. In this example, the ratio of N-to-N−1 is 5:4. Clock A corresponds to the higher clock domain and clock B corresponds to the lower clock domain. This means that for every 5 clock A cycles there will be 4 clock B cycles. In the higher frequency clock domain, it is known by the upstream logic that on a particular cycle, data cannot be transferred from the clock A domain to the clock B domain. This can be better understood from the timing diagram of FIG. 2.

#FIG. 2 shows the relationship between clocks A and B 21 and 22, respectively, the Data In 23, which is data being clocked into the synchronizer 1 at the clock A rate, and Data Out 24, which is data being clocked out of the synchronizer 1 and the clock B rate. In the example shown in FIG. 2, the upstream logic knows that it cannot send the “B” data of the Data In 23 and therefore will either continue sending the A data that proceeds the B data for two clock A cycles or will send the A data for one clock A cycle and the C data for two clock cycles. This will occur whenever the rising edges of clocks A and B line 20 up, which corresponds to edges 26A and 26B and edges 27A and 27B in FIG. 2. Thus, where clocks A and B are aligned at edges 26A and 26B, the D1 signal 25, which corresponds to the output of flip flop 5 in FIG. 1, will be held at the value of the A data for two clock A cycles. Similarly, where clocks A and B are aligned at edges 27A and 27B, the D1 signal 25 corresponding to the output of flip flop 5 in FIG. 1 will be held at the value of the F data for two clock A cycles. Therefore, neither the B or G data received at the Data In terminal 2 will propagate through to the output of the flip flop 5, which corresponds to the D1 signal.

#However the D0 signal is output from the flip flop 7 at the clock A rate because the flip flop 6 outputs a signal whenever the clock A signal is high and the flip flop 7 outputs a signal whenever the clock A signal is low due to the inverter 4. Since there are two latches 6 and 7 placed in series that receive the data from the clock A frequency domain, the output DO 26 will be delayed by one and one half clock cycles.