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US 2003/0141903 A1Published application
Clocked full-rail differential logic with sense amplifiers
AssigneeSun Microsystems, Inc.
InventorsSwee Yew Choe, Edgardo Klass
Life of this patent
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Abstract
Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.
Claims20
A cascaded chain of modified full-rail differential logic circuits comprising:
- a first modified full-rail differential logic circuit, said first modified full-rail differential logic circuit comprising:
- a first modified full-rail differential logic circuit first clock input terminal;
- a first modified full-rail differential logic circuit second clock input terminal;
- at least one first modified full-rail differential logic circuit data input terminal;
- and
- at least one first modified full-rail differential logic circuit data output terminal;
- a second modified full-rail differential logic circuit, said second modified full-rail differential logic circuit comprising:
- a second modified full-rail differential logic circuit first clock input terminal;
- a second modified full-rail differential logic circuit second clock input terminal;
- at least one second modified full-rail differential logic circuit data input terminal;
- and
- at least one second modified full-rail differential logic circuit data output terminal;
- a first clock signal coupled to said first modified full-rail differential logic circuit first clock input terminal;
- a second clock signal coupled to said second modified full-rail differential logic circuit first clock input terminal and said first modified full-rail differential logic circuit second clock input terminal, wherein;
- said at least one first modified full-rail differential logic circuit data output terminal is coupled to said at least one second modified full-rail differential logic circuit data input terminal, further wherein;
- said second clock signal is delayed with respect to said first clock signal by a predetermined delay time.
13 more elements
A cascaded chain of modified full-rail differential logic circuits comprising:
- a first supply voltage;
- a second supply voltage;
- a first modified full-rail differential logic circuit, said first modified full-rail differential logic circuit comprising:
- a first modified full-rail differential logic circuit out terminal;
- a first modified full-rail differential logic circuit outBar terminal;
- a first modified full-rail differential logic circuit first node, said first modified full-rail differential logic circuit first node being coupled to said first supply voltage;
- a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said first modified full-rail differential logic circuit first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said first modified full-rail differential logic circuit out terminal;
- a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said first modified full-rail differential logic circuit first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said first modified full-rail differential logic circuit outBar terminal;
- a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said first modified full-rail differential logic circuit outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said first modified full-rail differential logic circuit out terminal;
- a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode;
- said fourth transistor first flow electrode being coupled to said first modified full-rail differential logic circuit first node, said fourth transistor second flow electrode being coupled to said first modified full-rail differential logic circuit out terminal, said fourth transistor control electrode being coupled to a first clock signal;
- a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode;
- said fifth transistor first flow electrode being coupled to said first modified full-rail differential logic circuit first node, said fifth transistor second flow electrode being coupled to said first modified full-rail differential logic circuit outBar terminal, said fifth transistor control electrode being coupled to said first clock signal;
- a first modified full-rail differential logic circuit sense amplifier circuit coupled between said first modified full-rail differential logic circuit out terminal and said first modified full-rail differential logic circuit outBar terminal, said first modified full-rail differential logic circuit sense amplifier circuit having an input terminal coupled to a second clock signal;
- a logic block, said logic block comprising:
- at least one logic block input terminal;
- a logic block out terminal;
- and a logic block outBar terminal, said logic block out terminal being coupled to said first modified full-rail differential logic circuit out terminal and said logic block outBar terminal being coupled to said first modified full-rail differential logic circuit outBar terminal;
- a second modified full-rail differential logic circuit, said second modified full-rail differential logic circuit comprising:
- a second modified full-rail differential logic circuit out terminal;
- a second modified full-rail differential logic circuit outBar terminal;
- a second modified full-rail differential logic circuit first node, said second modified full-rail differential logic circuit first node being coupled to said first supply voltage;
- a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said second modified full-rail differential logic circuit first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said second modified full-rail differential logic circuit out terminal;
- a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said second modified full-rail differential logic circuit first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said second modified full-rail differential logic circuit outBar terminal;
- a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said second modified full-rail differential logic circuit outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said second modified full-rail differential logic circuit out terminal;
- a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode;
- said fourth transistor first flow electrode being coupled to said second modified full-rail differential logic circuit first node, said fourth transistor second flow electrode being coupled to said second modified full-rail differential logic circuit out terminal, said fourth transistor control electrode being coupled to said second clock signal;
- a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode;
- said fifth transistor first flow electrode being coupled to said second modified full-rail differential logic circuit first node, said fifth transistor second flow electrode being coupled to said second modified full-rail differential logic circuit outBar terminal, said fifth transistor control electrode being coupled to said second clock signal;
- a second modified full-rail differential logic circuit sense amplifier circuit coupled between said second modified full-rail differential logic circuit out terminal and said second modified full-rail differential logic circuit outBar terminal, said second modified full-rail differential logic circuit sense amplifier circuit having an input terminal coupled to a third clock signal;
- a logic block, said logic block comprising:
- at least one logic block input terminal;
- a logic block out terminal;
- and a logic block outbar terminal, said logic block out terminal being coupled to said second modified full-rail differential logic circuit out terminal and said logic block outBar terminal being coupled to said second modified full-rail differential logic circuit outBar terminal, wherein;
- said second clock signal is delayed with respect to said first clock signal by a predetermined delay time and said third clock signal is delayed with respect to said second clock signal by a predetermined delay time.
32 more elements
A modified full-rail differential logic circuit comprising:
- a first supply voltage;
- a second supply voltage;
- a modified full-rail differential logic circuit out terminal;
- a modified full-rail differential logic circuit outBar terminal;
- a modified full-rail differential logic circuit first node, said modified full-rail differential logic circuit first node being coupled to said first supply voltage;
- a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode, said modified full-rail differential logic circuit first node being coupled to said first transistor first flow electrode, said first transistor second flow electrode being coupled to said modified full-rail differential logic circuit out terminal;
- a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode, said modified full-rail differential logic circuit first node being coupled to said second transistor first flow electrode, said second transistor second flow electrode being coupled to said modified full-rail differential logic circuit outBar terminal;
- a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode, said first transistor control electrode being coupled to said third transistor first flow electrode and said modified full-rail differential logic circuit outBar terminal, said second transistor control electrode being coupled to said third transistor second flow electrode and said modified full-rail differential logic circuit out terminal;
- a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode;
- said fourth transistor first flow electrode being coupled to said modified full-rail differential logic circuit first node, said fourth transistor second flow electrode being coupled to said modified full-rail differential logic circuit out terminal, said fourth transistor control electrode being coupled a first clock signal;
- a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode;
- said fifth transistor first flow electrode being coupled to said modified full-rail differential logic circuit first node, said fifth transistor second flow electrode being coupled to said modified full-rail differential logic circuit outBar terminal, said fifth transistor control electrode being coupled said first clock signal;
- a modified full-rail differential logic circuit sense amplifier circuit coupled between said modified full-rail differential logic circuit out terminal and said modified full-rail differential logic circuit outBar terminal, said modified full-rail differential logic circuit sense amplifier circuit having an input terminal coupled to a second clock signal;
- a logic block, said logic block comprising:
- at least one logic block input terminal;
- a logic block out terminal;
- and a logic block outBar terminal, said logic block out terminal being coupled to said modified full-rail differential logic circuit out terminal and said logic block outBar terminal being coupled to said modified full-rail differential logic circuit outBar terminal, wherein;
- said second clock signal is delayed with respect to said first clock signal by a predetermined time.
15 more elements
Dependencies are inferred from the claim text.