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US 2003/0141902 A1Published application
Method for increasing the load capacity of full-rail differential logic
AssigneeSun Microsystems, Inc.
InventorsSwee Yew Choe, Edgardo Klass
Life of this patent
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Abstract
Modified full-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. Consequently, the modified full-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.
Claims6
A method for cascading a chain of modified full-rail differential logic circuits comprising:
- providing a first modified full-rail differential logic circuit, said first modified full-rail differential logic circuit comprising:
- a first modified full-rail differential logic circuit first clock input terminal;
- a first modified full-rail differential logic circuit second clock input terminal;
- at least one first modified full-rail differential logic circuit data input terminal;
- and
- at least one first modified full-rail differential logic circuit data output terminal;
- providing a second modified full-rail differential logic circuit, said second modified full-rail differential logic circuit comprising:
- a second modified full-rail differential logic circuit first clock input terminal;
- a second modified full-rail differential logic circuit second clock input terminal;
- at least one second modified full-rail differential logic circuit data input terminal;
- and
- at least one second modified full-rail differential logic circuit data output terminal;
- coupling a first clock signal to said first modified full-rail differential logic circuit first clock input terminal;
- coupling a second clock signal to said second modified full-rail differential logic circuit first clock input terminal;
- coupling said second clock signal to said first modified full-rail differential logic circuit second clock input terminal;
- coupling said at least one first modified full-rail differential logic circuit data output terminal to said at least one second modified full-rail differential logic circuit data input terminal;
- and
- delaying said second clock signal with respect to said first clock signal by a predetermined delay time.
15 more elements
A method of cascading a chain of modified full-rail differential logic circuits comprising:
- providing a first supply voltage;
- providing a second supply voltage;
- providing a first modified full-rail differential logic circuit by the method of:
- providing a first modified full-rail differential logic circuit out terminal;
- providing a first modified full-rail differential logic circuit outBar terminal;
- providing a first modified full-rail differential logic circuit first node;
- coupling said first modified full-rail differential logic circuit first node to said first supply voltage;
- providing a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode;
- coupling said first modified full-rail differential logic circuit first node to said first transistor first flow electrode;
- coupling said first transistor second flow electrode to said first modified full-rail differential logic circuit out terminal;
- providing a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode;
- coupling said first modified full-rail differential logic circuit first node to said second transistor first flow electrode;
- coupling said second transistor second flow electrode to said first modified full-rail differential logic circuit outBar terminal;
- providing a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode;
- coupling said first transistor control electrode to said third transistor first flow electrode and said first modified full-rail differential logic circuit outBar terminal;
- coupling said second transistor control electrode to said third transistor second flow electrode and said first modified full-rail differential logic circuit out terminal;
- providing a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode;
- coupling said fourth transistor first flow electrode to said first modified full-rail differential logic circuit first node;
- coupling said fourth transistor second flow electrode to said first modified full-rail differential logic circuit out terminal;
- providing a first clock signal;
- coupling said fourth transistor control electrode to said first clock signal;
- providing a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode;
- coupling said fifth transistor first flow electrode to said first modified full-rail differential logic circuit first node;
- coupling said fifth transistor second flow electrode to said first modified full-rail differential logic circuit outBar terminal;
- coupling said fifth transistor control electrode to said first clock signal;
- providing a second clock signal;
- coupling a first modified full-rail differential logic circuit sense amplifier circuit between said first modified full-rail differential logic circuit out terminal and said first modified full-rail differential logic circuit outBar terminal, said first modified full-rail differential logic circuit sense amplifier circuit having an input terminal coupled to said second clock signal;
- providing a logic block, said logic block comprising:
- at least one logic block input terminal;
- a logic block out terminal;
- and a logic block outBar terminal;
- coupling said logic block out terminal to said first modified full-rail differential logic circuit out terminal;
- coupling said logic block outBar terminal to said first modified full-rail differential logic circuit outBar terminal;
- providing a second modified full-rail differential logic circuit by the method of:
- providing a second modified full-rail differential logic circuit out terminal;
- providing a second modified full-rail differential logic circuit outBar terminal;
- providing a second modified full-rail differential logic circuit first node;
- coupling said second modified full-rail differential logic circuit first node to said first supply voltage;
- providing a first transistor, said first transistor comprising a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode;
- coupling said second modified full-rail differential logic circuit first node to said first transistor first flow electrode;
- coupling said first transistor second flow electrode to said second modified full-rail differential logic circuit out terminal;
- providing a second transistor, said second transistor comprising a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode;
- coupling said second modified full-rail differential logic circuit first node to said second transistor first flow electrode;
- coupling said second transistor second flow electrode to said second modified full-rail differential logic circuit outBar terminal;
- providing a third transistor, said third transistor comprising a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode;
- coupling said first transistor control electrode to said third transistor first flow electrode and said second modified full-rail differential logic circuit outBar terminal;
- coupling said second transistor control electrode to said third transistor second flow electrode and said second modified full-rail differential logic circuit out terminal;
- providing a fourth transistor, said fourth transistor comprising a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode;
- coupling said fourth transistor first flow electrode to said second modified full-rail differential logic circuit first node;
- coupling said fourth transistor second flow electrode to said second modified full-rail differential logic circuit out terminal;
- coupling said fourth transistor control electrode to said second clock signal;
- providing a fifth transistor, said fifth transistor comprising a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode;
- coupling said fifth transistor first flow electrode to said second modified full-rail differential logic circuit first node;
- coupling said fifth transistor second flow electrode to said second modified full-rail differential logic circuit outBar terminal;
- coupling said fifth transistor control electrode to said second clock signal;
- providing a third clock signal;
- coupling a second modified full-rail differential logic circuit sense amplifier circuit between said second modified full-rail differential logic circuit out terminal and said second modified full-rail differential logic circuit outBar terminal, said second modified full-rail differential logic circuit sense amplifier circuit having an input terminal;
- coupling said second modified full-rail differential logic circuit sense amplifier circuit input terminal to said third clock signal;
- providing a logic block, said logic block comprising:
- at least one logic block input terminal;
- a logic block out terminal;
- and a logic block outBar terminal;
- coupling said logic block out terminal to said second modified full-rail differential logic circuit out terminal;
- coupling said logic block outBar terminal to said second modified full-rail differential logic circuit outBar terminal;
- delaying said second clock signal with respect to said first clock signal by a predetermined delay time;
- and
- delaying said third clock signal with respect to said second clock signal by a predetermined delay time.
64 more elements
Dependencies are inferred from the claim text.