Programmable termination for CML I/O

Abstract

A programmable termination circuit (12) selectively providing a termination voltage to a driver or receiver of a high-speed serial link, such as CML I/O's. The programmable termination circuit (12) is adapted for use both at a transmitter front end (10) and at a receiver front-end (20) to selectively terminate the respective circuit to one of multiple available voltage supplies (VDDA, VDDT), such as 1.8 volts and 3.3 volts. The programmable termination circuit is software controllable via a single control signal (TS). A level shifter (14) circuit is provided for coupling the termination control signal (TS) to the programmable termination circuit (12) to level shift the termination control signal to a logic level suitable with large FETs (M1, M2) coupled to and controlling the connection of the voltage supplies. A back gate control circuit (40) is also provided to ensure that PMOS back gates of the large FETs (M1, M2) are tied to the highest supply available at any instant to avoid forward biasing of the diodes. The gate control circuit ensures that the gates of these PMOS devices are tied to the larger voltage supply should one supply be powered down.

Dependencies are inferred from the claim text.