US 2003/0141603 A1 · Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

Abstract

A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Claims20

Dependent claims

A semiconductor device comprising;

a semiconductor element having a plurality of electrodes;
a passivation film formed on said semiconductor element in a region avoiding at least a part of each of said electrodes;
a conductive foil provided at a given spacing from the surface on which said passivation film is formed;
external electrodes formed on said conductive foil;
an intermediate layer formed between said passivation film and said conductive foil to support said conductive foil;
and
wires electrically connecting said electrodes to said conductive foil;
wherein a depression tapered in a direction from said conductive foil to said passivation film is formed in said intermediate layer under a part of said conductive foil that includes the connection with said external electrodes.

5 more elements

A method of manufacturing a semiconductor device, comprising the steps of;

providing a semiconductor element that includes a plurality of electrodes and a passivation film that is formed on a surface of said semiconductor element in a region avoiding at least a part of each of said electrodes;
forming a conductive foil at a given spacing from the surface on which said passivation film is formed, an intermediate layer between said passivation film and said conductive foil to support said conductive foil, and a depression in said intermediate layer in a position to avoid said electrodes;
forming wires that connect electrically raid electrode to said conductive foil;
and
forming external electrodes on said conductive foil in a position above said depression.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

10/383,530Filed 10 Mar 2003

Priority

JP 10-09400723 Mar 1998

Published

31 Jul 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10W 74/111
Characterised by their shape or disposition: the semiconductor body being completely enclosed
H10W 72/20
Interconnections or connectors in packages: bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
H10W 74/129
The semiconductor body being completely enclosed: forming a chip-scale package [CSP]
H10W 90/701
Package configurations: characterised by the relative positions of pads or connectors relative to package parts

Family

Application09/272,244Continuation · filed 19 Mar 1999

Application09/985,074Continuation · filed 1 Nov 2001

Application10/383,530Continuation · filed 10 Mar 2003

US 2002/0030288 A1Published application

US 6,333,565 B1Related patent

US 6,583,516 B2Related patent

US 6,900,548 B2Related patent

US 2003/0141603 A1This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

Life of this patent

Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

Life of this patent

Abstract

Claims20