Layout structure and method for supporting two different package techniques of CPU

A motherboard for supporting a plurality of CPUs of two different package techniques, comprising:

• a first area, used to place said CPU;
• a second area, located in between said CPU and a control chip, comprising:
• a top signal layer, used to place a first signal line in said area where said CPU is coupled to the control chip;
• a reference potential providing layer, located below said top signal layer, coupled to a reference potential, wherein said first signal line refers to the reference potential providing layer;
• a power layer, located below said reference potential providing layer, comprising:
• a voltage providing area for providing an operating voltage to the CPU and said control chip;
• and
• a reference potential providing area, coupled to the reference potential;
• and
• a bottom signal layer, located below said power layer, used to place a second signal line in said area where said CPU is coupled to the control chip, wherein said second signal line refers to the reference potential providing area in said power layer.

A layout structure for supporting a plurality of central processing units (CPUs) of two different package techniques, placed and coupled with a first area, wherein said first area is said area where a plurality of signals of a CPU is coupled to a plurality of signals of a control chip, said structure comprising:

• a first signal layer;
• a first reference layer, having a first reference potential, wherein a first signal line that is placed on said first signal layer refers to the first reference layer;
• a second reference layer, comprising:
• a first reference area, having said first reference potential;
• and
• a second reference area, having a second reference potential, used to provide an operating voltage that is needed for said CPU;
• and
• a second signal layer, wherein a second signal line that is placed on said second signal layer refers to the first reference area of said second reference area.

A motherboard for supporting a plurality of CPUs of two different package techniques, placed between a CPU and a control chip, comprising:

• a first area, wherein said whole CPU is placed in said range of said first area, said stack structure of said first area along a first direction sequentially comprising:
• a first signal layer;
• a first reference layer, having a first reference potential;
• a second reference layer, comprising:
• a first reference area, having said first reference potential;
• and
• a second reference area, having a second reference potential;
• and
• a second signal layer;
• a second area, all said plurality of signals of said control chip that are coupled to the CPU are placed in said range of said second area, said stack structure of said second area along said first direction sequentially comprising:
• a third signal layer;
• a third reference layer, having said first reference potential;
• a fourth reference layer, comprising:
• a third reference area, having said first reference potential;
• and
• a fourth reference area, having said second reference potential;
• and
• a fourth signal layer;
• and
• a third area, all said plurality of signals of said control chip that are not coupled to the CPU are placed in said range of said third area, said stack structure of said third area along said first direction sequentially comprising:
• a fifth signal layer;
• a fifth reference layer, having said first reference potential;
• a sixth reference layer, having a plurality of reference areas that have a plurality of other reference potentials;
• and
• a sixth signal layer.

A layout method for supporting a plurality of CPUs of different package techniques, comprising:

• providing a plurality of printed circuit boards;
• placing on said printed circuit board that is used to constitute a top signal layer and a bottom signal layer, wherein said placement can be processed on said top signal layer and said bottom signal layer in said area where said control chip is coupled to the CPU;
• cutting said printed circuit board that is used to constitute a power layer to cut off an area that is coupled to a reference potential on said power layer in said area where said control chip is coupled to the CPU;
• and
• combining said printed circuit board to form a stack structure.