Metal oxide semiconductor field-effect transistor and associated methods
AssigneeSTMicroelectronics S.r.I.
InventorsAlessandro Moscatelli, Giuseppe Croce
Life of this patent
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Abstract
A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.
Claims50
Metal oxide semiconductor transistor (100;
- 200;
- 300;
- 400;
- 600) integrated in a wafer of semiconductor material (30;
- 31) and comprising a gate structure (3, 11;
- 32, 35) located on one surface (10b;
- 45) of the said wafer and including an insulating gate layer (3;
- 32),
- characterized in that the said insulating gate layer (3;
- 32) includes a first portion (4;
- 41) having a first thickness (t1;
- T1) and a second portion (5;
- 42) having a second thickness (t2;
- T2) differing from the first thickness.
Method for manufacturing a metal oxide semiconductor field-effect transistor (100;
- 200;
- 300) integrated in a wafer (30) of semiconductor material, the said method comprising a stage of forming a layer of gate oxide (3) on one surface (10b) of the said wafer;
- characterized in that the said layer of gate oxide
- (3) includes a first portion (4) having a first thickness (t1) and a second portion (5) having a second thickness (t2) differing from the first thickness.
Structure integrated in a wafer (30) of semiconductor material, the said structure comprising:
- at least one MOS field-effect transistor (400) including an active region (37, 38) which forms an active area (33) on a surface of the wafer, and a silicide surface layer which at least partially covers the said first active area,
- characterized in that it also comprises at least one LDMOS transistor (300) including a first active region (26) which forms a first active area (19) on the surface of the wafer, and a first silicide surface layer (24) which only partially covers the said first active area.
Method of manufacturing at least one MOS field-effect transistor (400) and at least one LDMOS field-effect transistor (300) integrated in a wafer (30) of semiconductor material, the said method comprising the stages of:
- a) forming in the wafer (30) two active regions (37, 38, 39, 34) of the said at least one MOS transistor (400), the said active regions forming corresponding active areas (33, 34) on the surface of the wafer,
- b) forming in the wafer (30) a first (26) and a second (27) active region of the said at least one LDMOS transistor (300), the said first and second active regions forming a first and a second active area (19;
- 20) on a surface of the wafer,
- c) forming a layer of silicide on at least one portion of each of the two active areas (33, 34) of the said at least one MOS transistor (600),
- d) forming a first (24) and a second (22) layer of silicide on the said first (19) and second (20) active area of the at least one LDMOS transistor (300), the said first layer of silicide (24) only partially covering the first active area (19).
Dependencies are inferred from the claim text.