Semiconductor integrated circuit device and a method of manufacturing thereof

A semiconductor integrated circuit device comprising:

• a first MISFET formed on a substrate in a first active region whose periphery is defined by an element isolation trench;
• and
• a second MISFET formed on the substrate in a second active region whose periphery is defined by the element isolation trench,
• wherein a first gate electrode of said first MISFET, which crosses the first active region so as to extend from one end thereof to the other end thereof, is formed on the substrate in the first active region,
• a second gate electrode of said second MISFET, which crosses the second active region so as to extend from one end thereof to the other end thereof, is formed on the substrate in the second active region,
• a gate length of the first gate electrode in a boundary region defined between the first active region and the element isolation trench is greater than a gate length thereof in a central portion of the first active region, and
• a gate length of the second gate electrode in a boundary region defined between the second active region and the element isolation trench is substantially equal to a gate length thereof in a central portion of the second active region.

A semiconductor integrated circuit device comprising:

• a memory cell comprised of a pair of drive MISFETs, a pair of load MISFETs and a pair of transfer MISFETs,
• said each drive MISFET being formed on a substrate in a first active region whose periphery is defined by an element isolation trench,
• wherein a gate electrode of said each drive MISFET, which crosses the first active region so as to extend from one end thereof to the other end thereof, is formed on the substrate in the first active region, and
• a gate length of the gate electrode in a boundary region defined between the first active region and the element isolation trench is greater than a gate length thereof in a central portion of the first active region.

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming trenches in a substrate in a region exposed from an insulating film formed on the substrate;
• (b) forming a silicon oxide film on the insulating film including the interiors of the trenches and thereafter removing the silicon oxide film lying outside said each trench by chemical mechanical polishing with the insulating film as a stopper, thereby forming element isolation trenches in the substrate in the element isolation region;
• (c) removing the insulating film and thereafter wet-etching the substrate, thereby reducing a step between the surface of said element isolation trench and the surface of the substrate in the active region whose periphery is defined by said element isolation trench;
• (d) introducing a first impurity for controlling a threshold voltage of a first MISFET into the substrate in the first active region;
• and
• (e) forming a first gate electrode of the first MISFET on the substrate in the first active region, said first gate electrode crossing the first active region so as to extend from one end thereof to the other end thereof, having a gate length in a boundary region defined between the first active region and the element isolation trench, which is greater than a gate length thereof in a central portion of the first active region, and covering the whole of one side extending along a gate-length direction, of the boundary region and parts of two sides thereof extending in a gate-width direction.

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) forming trenches in a substrate in an element isolation region by dry etching using a resistance-to-oxidation film formed on the substrate as a mask;
• (b) forming a silicon oxide film on the resistance-to-oxidation film including the interiors of the trenches and thereafter removing the silicon oxide film lying outside said each trench by chemical mechanical polishing with the resistance-to-oxidation film as a stopper, thereby forming element isolation trenches in the substrate in the element isolation region;
• (c) removing the resistance-to-oxidation film and thereafter wet-etching the substrate, thereby reducing a step between the surface of said element isolation trench and the surface of the substrate in each of the first and second active regions whose peripheries are defined by said element isolation trench;
• (d) introducing a first impurity for controlling a threshold voltage of a first MISFET into the substrate in the first active region and introducing a second impurity for controlling a threshold voltage of a second MISFET into the substrate in the second active region;
• and
• (e) forming a first gate electrode of the first MISFET on the substrate in the first active region, said first gate electrode crossing the first active region so as to extend from one end thereof to the other end thereof and having a gate length in a boundary region defined between the first active region and the element isolation trench, which is greater than a gate length thereof in a central portion of the first active region, and forming a second gate electrode of the second MISFET on the substrate in the second active region, said second gate electrode crossing the second active region so as to extend from one end thereof to the other end thereof and having a gate length in a boundary region defined between the second active region and the element isolation trench, which is substantially equal to a gate length in a central portion of the second active region.

A semiconductor integrated circuit device comprising:

• a first MISFET formed on a substrate in a first active region whose periphery is surrounded by an element isolation trench;
• and
• a second MISFET formed on the substrate in a second active region whose periphery is defined by the element isolation trench,
• wherein a first gate electrode of said first MISFET, which crosses the first active region so as to extend from one end thereof to the other end thereof, is formed on the substrate in the first active region,
• a second gate electrode of said second MISFET, which crosses the second active region so as to extend from one end thereof to the other end thereof, is formed on the substrate in the second active region,
• a gate length of the first gate electrode in a boundary region defined between the first active region and the element isolation trench is greater than a gate length thereof in a central portion of the first active region, and
• a gate length of the first gate electrode in a boundary region defined between the first active region and the element isolation trench is greater than a gate length of the second gate electrode in a boundary region defined between the second active region and the element isolation trench.

A semiconductor integrated circuit device comprising:

• a first MISFET formed on a substrate in a first active region whose periphery is defined by an element isolation trench;
• and
• a second MISFET formed on the substrate in a second active region whose periphery is defined by the element isolation trench,
• wherein a first gate electrode of said first MISFET, which crosses the first active region so as to extend from one end thereof to the other end thereof, is formed on the substrate in the first active region,
• a gate length of the first gate electrode in a boundary region defined between the first active region and the element isolation trench is greater than a gate length in a central portion of the first active region,
• said first gate electrode in the boundary region covers the whole of one side extending in a gate-length direction, of the boundary region, and parts of two sides thereof extending in a gate-width direction,
• a second gate electrode of said second MISFET, which crosses the second active region so as to extend from one end thereof to the other end thereof, is formed on the substrate in the second active region,
• a gate length of the second gate electrode in a boundary region defined between the second active region and the element isolation trench is greater than a gate length in a central portion of the second active region,
• said second gate electrode in the boundary region covers the whole of one side extending in a gate-length direction, of the boundary region, and parts of two sides thereof extending in a gate-width direction,
• said first active region is formed in a first well region of a first conduction type,
• said second active region is formed in a second well region of a first conduction type, and
• said first well region and said second well region are formed electrically separately from each other.