US 2003/0141553 A1Published application

Field effect transistor formed on SOI substrate

AssigneeOki Electric Industry Co., Ltd.

InventorNoriyuki Miura

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Abstract

A field effect transistor comprises a silicon layer formed on an insulator, a diffused layer formed by diffusing dopant from a part of a surface of the silicon layer up to the insulator, a silicide layer formed toward the insulator side from a surface of the diffused layer so as to have a thickness less than or equal to that of the diffused layer, a contact conductive layer formed on the surface of the silicide layer, a gate insulating layer formed on the silicon layer, a gate electrode formed on the gate insulating layer and a sidewall formed on a side surface of the gate electrode. The shortest distance X between surfaces opposed to each other, of the contact conductive layer and the sidewall satisfies a relation represented by the following expression (1): R(slc)×106×(1+Tslc/Tsoi)≦X≦200/rs. Expression (1)

Claims21

Dependent claims

A field effect transistor comprising:

a silicon layer formed on an insulator;
a diffused layer formed by diffusing dopant from a part of a surface of the silicon layer up to the insulator;
a silicide layer formed toward the insulator side from a surface of the diffused layer so as to have a thickness less than or equal to that of the diffused layer;
a contact conductive layer formed on the surface of the silicide layer;
a gate insulating layer formed on the silicon layer;
a gate electrode formed on the gate insulating layer;
and
a sidewall formed on a side surface of the gate electrode;
wherein the shortest distance X between surfaces opposed to each other, of the contact conductive layer and the sidewall satisfies a relation represented by the following expression (1):
R(slc)×106×(1+Tslc/Tsoi)≦X≦200/rs Expression (1)
where in the expression (1), X indicates the shortest distance (μm) between the mutually-opposed surfaces of the contact conductive layer and the sidewall, R(slc) indicates a contact resistance (Ω·cm2) of a boundary surface between the silicide layer and the diffused layer, Tslc indicates the thickness (μm) of the silicide layer, Tsoi indicates the thickness (μm) of the silicon layer, and rs indicates a series resistance (Ω/) of the silicide layer.

8 more elements

A field effect transistor formed on a semiconductor layer having a thickness of Tsoi μm, the field effect transistor comprising:

a silicide layer formed on the semiconductor layer, the silicide layer having a thickness of Tslc μm and a series resistance of rs Ω/;
a diffusion layer formed in contact with the silicide layer so as to form a boundary surface between the silicide layer and the diffused layer, the boundary surface having a contact resistance of R(slc) Ω·cm2;
a contact conductive layer formed on the silicide layer;
a gate insulating layer formed on the semiconductor layer;
a gate electrode formed on the gate insulating layer, the gate electrode having a side surface thereof;
and
a sidewall formed on the side surface of the gate electrode, the sidewall and the contact conductive layer having a minimum distance of X μm, wherein the X satisfies a relation represented by the following expression (1).
R(slc)×106×(1+Tslc/Tsoi)≦X≦200/rs Expression (1):

5 more elements

A field effect transistor comprising:

an SOI substrate having an insulator layer and a semiconductor layer formed on the insulator layer, the semiconductor layer having a thickness of Tsoi μm;
a silicide layer formed in the semiconductor layer, the silicide layer having a thickness of Tslc μm and a series resistance of rs Ω/;
a diffusion layer formed in contact with the silicide layer so as to form a boundary surface between the silicide layer and the diffused layer, the boundary surface having a contact resistance of R(slc) Ω·cm2;
a contact conductive layer formed on the silicide layer;
a gate insulating layer formed on the semiconductor layer;
a gate electrode formed on the gate insulating layer, the gate electrode having a side surface thereof;
and
a sidewall formed on the side surface of the gate electrode, the sidewall and the contact conductive layer having a minimum distance of X μm, wherein the X satisfies a relation represented by the following expression (1).
R(slc)×106×(1+Tslc/Tsoi)≦X≦200/rs Expression (1):

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/284,203Filed 31 Oct 2002
Priority: JP 023279/200231 Jan 2002
Published: 31 Jul 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 30/6737
Characterised by the electrodes: characterised by the electrode materials
H10D 30/6713
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device:…
H10D 30/6729
Thin-film transistors [TFT]: characterised by the electrodes
H10D 30/6743
Group IV materials, e.g. germanium or silicon carbide: silicon