Transistor with reduced short channel effects and method

A method of fabricating a transistor comprising:

• forming a gate structure outwardly of a substrate;
• forming initial sidewalls outwardly of the substrate and substantially adjacent to the gate structure;
• forming source and drain regions in the substrate using the initial sidewalls as a mask;
• forming additional sidewalls substantially adjacent to the initial sidewalls;
• and
• forming deep blanket source and drain regions in said substrate using the initial sidewalls and the additional sidewalls as a mask.

A method of fabricating a transistor, comprising:

• forming a gate structure outwardly of a substrate;
• forming initial sidewalls outwardly of the substrate and substantially adjacent to the gate structure, the initial sidewalls having a width;
• forming deep blanket source and drain regions in the substrate using the initial sidewalls as a mask;
• reducing the width of the initial sidewalls to form reduced-width sidewalls;
• and
• forming source and drain regions in the substrate using the reduced-width sidewalls as a mask.

A semiconductor device comprising a plurality of metal oxide semiconductor field effect transistors (MOSFETs), at least a portion of the MOSFETs comprising:

• a channel;
• source and drain regions substantially adjacent to the channel;
• and
• deep blanket source and drain regions substantially adjacent to the channel, wherein a shortest distance across the channel between the source and drain regions is no greater than a shortest distance across the channel between the deep blanket source and drain regions.