Dual-bit flash memory cells for forming high-density memory arrays

A scalable dual-bit flash memory array, comprising:

• a semiconductor substrate of a first conductivity type;
• a plurality of gate regions and a plurality of common bus-line regions being formed alternately over said semiconductor substrate and transversely to the plurality of parallel STI regions, wherein the plurality of gate regions are formed by a masking photoresist step and are therefore scalable;
• a plurality of common-source diffusion regions of a second conductivity type being formed in said semiconductor substrate of the plurality of active regions along the plurality of common bus-line regions, wherein said common-source diffusion region comprises a heavily-doped diffusion region being formed within a lightly-doped diffusion region;
• a first flat bed being formed between a pair of dielectric-spacer structures in each of the plurality of common bus-line regions and being formed alternately by said common-source diffusion region and a first etched raised field-oxide layer, wherein each of said dielectric-spacer structures comprises from top to bottom a sidewall dielectric spacer, a poly-oxide layer, and a conductive erasing anode, and each of the plurality of common bus-line regions comprises from top to bottom a planarized thick-oxide layer being formed over said pair of dielectric spacer structures, a silicide layer, and a common conductive bus line formed over said first flat bed and integrated with said conductive erasing anodes;
• a stack-gate transistor region being formed in each side portion of said gate region and a select-transistor region being formed between said stack-gate transistor regions, wherein said stack-gate transistor region comprises from top to bottom a sidewall dielectric spacer being formed over a nearby sidewall of said common bus-line region, an elongated control-gate layer being formed over an intergate dielectric layer, and a plurality of integrated floating-gate layers, and said select-transistor region comprises a plurality of planarized conductive islands being formed over a gate-dielectric layer formed on a second flat bed formed alternately by a second etched raised field-oxide layer and an implanted semiconductor region;
• and
• a plurality of word lines being formed alternately above the plurality of active regions and transversely to the plurality of parallel STI regions and being electrically connected to the plurality of planarized conductive islands along the plurality of active regions, wherein each of the plurality of word lines is formed by a metal layer together with the plurality of planarized conductive islands being simultaneously patterned and etched by a hard masking layer including a masking dielectric layer and its two sidewall dielectric spacers.

A scalable dual-bit flash memory array, comprising:

• a semiconductor substrate of a first conductive type;
• a plurality of gate regions and a plurality of common bus-line regions being formed alternately over said semiconductor substrate and transversely to the plurality of parallel STI regions, wherein the plurality of gate regions are formed by a masking photoresist step and are therefore scalable;
• a plurality of common-source diffusion regions of a second conductivity type being formed in said semiconductor substrate of the plurality of active regions along the plurality of common bus-line regions, wherein said common-source diffusion region comprises a heavily-doped diffusion region being formed within a lightly-doped diffusion region;
• a first flat bed being formed between a pair of dielectric-spacer structures in each of the plurality of common bus-line regions and being formed alternately by said common-source diffusion region and a first etched raised field-oxide layer, wherein each of said dielectric-spacer structures comprises from top to bottom a sidewall dielectric spacer, a poly-oxide layer, and a conductive erasing anode, and each of the plurality of common bus-line regions comprises from top to bottom a planarized thick-oxide layer being formed over said pair of dielectric-spacer structures, a silicide layer, and a common conductive bus-line being formed over said first flat bed and integrated with said conductive erasing anodes;
• a stack-gate transistor region being formed in each side portion of said gate region and a select region being formed between said stack-gate transistor regions, wherein said stack-gate transistor region comprises from top to bottom a sidewall dielectric spacer being formed over a nearby sidewall of said common bus-line region, an elongated control-gate layer being formed over an intergate dielectric layer, and a plurality of integrated floating-gate layers, and said select region comprises a plurality of planarized conductive islands being formed between a pair of sidewall dielectric spacers being formed over the inner sidewalls of said stack-gate transistor regions and on a second flat bed being formed alternately by a second etched raised field-oxide layer and a common-drain diffusion region;
• and
• a plurality of bit lines being formed alternately above the plurality of active regions and transversely to the plurality of parallel STI regions and being electrically connected to the plurality of planarized conductive islands along the plurality of active regions, wherein each of the plurality of bit lines is formed by a metal layer together with the plurality of planarized conductive islands being simultaneously patterned and etched by a hard masking layer including a masking dielectric layer and its two sidewall spacers.