Method of fabricating a polysilicon capacitor utilizing FET and bipolar base polysilicon layers
AssigneeInternational Business Machines Corporation
InventorsDouglas Duane Coolbaugh, Gregory Gower Freeman, Seshadri Subbanna
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Abstract
A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.
Claims30
A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of:
- depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor;
- and
- depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor,
- said second layer of polsilicon comprising SiGe polysilicon.
A method of forming a poly-poly capacitor comprising the steps of:
- (a) forming a film stack on a surface of a semiconductor structure, said structure comprising at least a gate region of a metal oxide semiconductor device and a bottom polysilicon plate of a poly-poly capacitor formed on a surface thereof, said film stack including at least a polysilicon layer;
- (b) forming a bipolar opening in said film stack exposing at least a portion of said surface of said semiconductor structure, wherein said bipolar opening is formed in a region in which a bipolar device will be subsequently fabricated;
- (c) simultaneously forming a SiGe epi layer in said bipolar opening, while forming a SiGe polysilicon film on exposed portions of said polysilicon layer of said film stack;
- (d) selectively doping portions of said SiGe polysilicon film as well as said SiGe epi layer with a dopant atom of a first conductivity type;
- (e) forming a patterned passivating layer on a portion of said doped SiGe epi layer;
- (f) forming a patterned doped emitter polysilicon layer on said patterned passivating layer as well as on said doped SiGe epi layer formed in said bipolar opening thereby completing fabrication of said bipolar device, said doped emitter polysilicon layer having a different conductivity than said doped SiGe epi layer;
- and
- (g) removing selective portions of said doped SiGe polysilicon film and remaining layers of said film stack so as to expose said gate of said metal oxide semiconductor while protecting said bipolar device region and said doped SiGe polysilicon layer overlying said bottom polysilicon plate of said poly-poly capacitor.
A poly-poly capacitor comprising two plate electrodes, wherein at least one of said plate electrodes is composed of SiGe polysilicon, said plate electrodes being separated by an insulator structure.
A semiconductor device, comprising
- a capacitor having first and second plate electrodes, one of said plate electrodes being comprised of a first conductive patterned layer;
- and
- a bipolar device having first and second electrodes, one of said electrodes being comprised of said first conductive patterned layer;
- wherein said first conductive patterned layer is comprised of SiGe material.
A semiconductor structure, comprising
- a first layer of polysilicon patterned to form a first electrode of a MOS device and a first plate electrode of a capacitor, and
- a second layer of SiGe polysilicon patterned to form a first electrode of a bipolar device and a second plate electrode of said capacitor,
- said second layer being comprised of SiGe polysilicon.
Dependencies are inferred from the claim text.