Ferroelectric integrated circuit devices having an oxygen penetration path and methods for manufacturing the same

A method of fabricating a ferroelectric integrated circuit device, the method comprising:

• forming at least one ferroelectric capacitor on an integrated circuit substrate;
• forming at least one oxygen penetration path layer on the at least ferroelectric capacitor;
• forming an encapsulated barrier layer on the at least one oxygen penetration path layer;
• forming an interlayer insulation layer on the encapsulated barrier layer;
• and
• forming a common via hole through the interlayer insulation layer, the encapsulated barrier layer and at least part of the oxygen penetration path layer to define an oxygen penetration path to a ferroelectric layer of the at least one ferroelectric capacitor through the at least one oxygen penetration path layer.

A ferroelectric memory device comprising:

• an underlying interlayer insulation layer formed on a semiconductor substrate;
• a plurality of ferroelectric capacitors arranged two-dimensionally on the underlying interlayer insulation layer in row and column directions;
• an encapsulated barrier layer indirectly wrapping the ferroelectric capacitors with an oxygen penetration path being interposed therebetween;
• a top interlayer insulation layer formed on the encapsulated barrier layer;
• and
• a plurality of plate lines parallel to the row direction and each electrically connected to at least two adjacent rows of ferroelectric capacitors.

A method of fabricating a ferroelectric memory device, the method comprising:

• (a) forming an underlying interlayer insulation layer on a semiconductor substrate;
• (b) forming a plurality of ferroelectric capacitors on the underlying interlayer insulation layer to be arranged two-dimensionally in row and column directions;
• and
• (c) forming an encapsulated barrier layer which indirectly wraps the ferroelectric capacitors with an oxygen penetration path being interposed therebetween and a plurality of plate lines which are parallel to the row direction and each of which is electrically connected to at least two adjacent rows of ferroelectric capacitors.