System and method for aligning an integrated circuit die on an integrated circuit substrate
AssigneeSTMicroelectronics S.r.l.
InventorsHarry Michael Siegel, Anthony M. Chiu
Life of this patent
Estimating the term…
Loading patent…
AssigneeSTMicroelectronics S.r.l.
InventorsHarry Michael Siegel, Anthony M. Chiu
Estimating the term…
A system and method is disclosed for aligning an integrated circuit die on an integrated circuit substrate. A plurality of deposits of deformable material are placed on the substrate where the integrated circuit die is to be aligned. In one advantageous embodiment a stamping tool is indexed to a first tooling hole and to a second tooling hole in the substrate. The stamping tool imprints the deposits of deformable material to a tolerance of less than one hundred microns with respect to the first and second tooling holes. The imprinted portions of the deposits to form a pocket for receiving the integrated circuit die. This enables the integrated circuit die to be precisely aligned on the substrate in three dimensions.
A stamping tool comprising:
A method for aligning an integrated circuit die on an integrated circuit substrate, the method comprising the steps of:
A method for aligning an integrated circuit die on an integrated circuit substrate of the type comprising a first tooling hole and a second tooling hole, the method comprising the steps of:
Dependencies are inferred from the claim text.