Multi-layer circuit assembly and process for preparing the same
AssigneePPG Industries Ohio, Inc.
InventorsKevin C. Olson, Alan E. Wang
Life of this patent
Estimating the term…
Abstract
Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.
Claims67
A process for fabricating a multi-layer circuit assembly comprising the following steps:
- (a) providing a substrate at least one area of which comprises a plurality of vias, said area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter);
- (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon;
- and
- (c) applying a layer of metal to all surfaces of the substrate.
A process for fabricating a multi-layer circuit assembly comprising the following steps:
- (a) providing a substrate at least one area of which comprises a plurality of vias, said area(s) having a via density of 500 to 10,000 holes per square inch (75 to 1550 holes per square centimeter;
- (b) applying a resist at predetermined locations on the substrate;
- (c) applying a dielectric coating onto all surfaces of the substrate of step (b) except at locations covered by said resist;
- (d) removing said resist at predetermined locations;
- and
- (e) applying a layer of metal to all surfaces of the substrate of step (d).
A process for fabricating a multi-layer circuit assembly comprising the following steps:
- (a) providing a substrate at least one area of which comprises a plurality of vias, said area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter);
- (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon;
- (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate;
- (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core;
- (e) applying a resist to the metal layer to form a photosensitive layer thereon;
- (f) imaging said resist in predetermined locations;
- (g) developing said resist to uncover selected areas of the metal layer;
- and
- (h) etching said uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.
A multi-layer circuit assembly comprising:
- (a) a substrate at least one area of which comprises a plurality of vias, said area having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter);
- (b) a dielectric coating applied onto all exposed surfaces of the substrate;
- (c) a layer of metal applied to all surfaces of substrate of step (b);
- and
- (d) a photosensitive layer applied to the metal layer.
Dependencies are inferred from the claim text.