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US 2003/0126580 A1Published application
High level synthesis method and apparatus
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsKeiichi Kurokawa, Osamu Ogawa
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AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsKeiichi Kurokawa, Osamu Ogawa
Estimating the term…
A behavioral description is converted to a CDFG. The CDFG is scheduled in such a way that the number of registers is minimized with a desired number of clock cycles. Hardware is allocated to the scheduled results. The minimum clock period (semi-synchronous minimum clock period) attainable by adjusting clock timings for allocated registers is determined. When the semi-synchronous minimum clock period is greater than a desired clock period, all the clock timings are reset to a same value and then the positions of the registers in the CDFG are so changed as to reduce the clock period. The processing returns to the step of determining the semi-synchronous minimum clock period when the performance is improved as a result of performing retiming, or otherwise is terminated.
A high level synthesis method for automatically generating a register transfer level circuit description from a behavioral circuit description, wherein clock timings for registers are synthesized simultaneously during the synthesis of the register transfer level circuit description from the behavioral circuit description.
A high level synthesis apparatus for automatically generating a register transfer level circuit description from a behavioral circuit description, wherein clock timings for registers are synthesized simultaneously during the synthesis of the register transfer level circuit description from the behavioral circuit description.
Dependencies are inferred from the claim text.