RC netlist reduction for timing and noise analysis
AssigneeSun Microsystems, Inc.
InventorXiao-Dong Yang
Life of this patent
Estimating the term…
Abstract
A circuit reduction method that generates a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics is provided. Further, a circuit reduction method that allows a user to selectively determine which nodes of an original circuit to reduce is provided. Further, a circuit reduction tool that is capable of removing loops that are not present in an original circuit but are present in an extraction of the original circuit is provided.
Claims24
A circuit reduction method, comprising:
- inputting information about an original circuit structure;
- using a resistive degree of at least one node in the original circuit structure to selectively sort the at least one node;
- determining at least one time constant of the original circuit;
- sorting the at least one time constant;
- and
- determining whether to remove a loop in the original circuit structure based on the sorted at least one time constant and the sorted at least one node.
A computer-readable medium having recorded therein instructions executable by processing, the instructions for:
- inputting information about an original circuit structure;
- using a resistive degree of at least one node in the original circuit structure to selectively sort the at least one node;
- determining at least one time constant of the original circuit;
- sorting the at least one time constant;
- and
- determining whether to remove a loop in the original circuit structure based on the sorted at least one time constant and the sorted at least one node.
A computer system, comprising:
- a processor;
- a memory;
- and
- instructions, residing in the memory and executable by the processor, for:
- inputting information about an original circuit structure;
- using a resistive degree of at least one node in the original circuit structure to selectively sort the at least one node;
- determining at least one time constant of the original circuit;
- sorting the at least one time constant;
- and
- determining whether to remove a loop in the original circuit structure based on the sorted at least one time constant and the sorted at least one node.
Dependencies are inferred from the claim text.