Apparatus, method and pattern for evaluating semiconductor device characteristics

A characteristic evaluation method for evaluating characteristics of a semiconductor device, the method comprising the steps of:

• obtaining an external resistance Rsd1, a gate contact length Lgc1 and a channel width W1 of a first evaluation pattern of MOSFETs;
• obtaining an external resistance Rsd2, a gate contact length Lgc2 and a channel width W2 of a second evaluation pattern of MOSFETs;
• and
• computing a sheet resistance Rsh and an overlapping portion resistance Rdsw of MOSFETs in accordance with expressions:
• Rsh=(W2·Rsd2−W1·Rsd1)/(Lgc2−Lgc1) Rdsw=(W1·Lgc2·Rsd1−W2·Lgc1·Rsd2)/(Lgc2−Lgc1)

A characteristic evaluation pattern for evaluating MOSFET characteristics, the pattern comprising:

• a first transistor;
• a second transistor having a gate-contact length equal to that of said first transistor and a gate length different from that of said first transistor;
• a third transistor having a gate-contact length different from that of said first transistor and a gate length equal to that of said first transistor;
• a gate terminal, a source terminal, a drain terminal, and a back gate terminal electrically conducting to a gate electrode, a source region, a drain region, and a back gate electrode of said first transistor respectively;
• a gate terminal, a source terminal, a drain terminal, and a back gate terminal electrically conducting to a gate electrode, a source region, a drain region, and a back gate electrode of said second transistor respectively;
• and
• a gate terminal, a source terminal, a drain terminal, and a back gate terminal electrically conducting to a gate electrode, a source region, a drain region, and a back gate electrode of said third transistor respectively.