Iterative concatenated code decoding circuit and encoding/decoding system using the same
AssigneeNEC Corporation
InventorKatutoshi Seki
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AssigneeNEC Corporation
InventorKatutoshi Seki
Estimating the term…
This invention provides an iterative concatenated code decoding circuit that allows a circuit size to be reduced and the error correction capability to be improved. A encoded data received through a transmission path from a first stage inner decoder is decoded, in which the decoded data is output to a first stage deinterleaver, and a first stage inner code syndrome coefficient corresponding to the decoded data is output to a second stage inner decoder. A first stage deinterleaver makes the deinterleaving of the decoded data, and outputs the deinterleaved data to a first stage outer decoder. The first stage outer decoder decodes the deinterleaved data and outputs the decoded data to a first stage interleaver, in which the first stage inner code modification syndrome coefficient is derived and output to a second stage inner decoder. The first stage interleaver makes the interleaving of the decoded data, and outputs the interleaved data to the second stage inner decoder.
An iterative concatenated code decoding circuit, employing a concatenated code concatenating two codes of an outer code and an inner code, in which an coding ratio of each of said inner code and said outer code is represented by (code-word length−redundancy check length)/(code-word length), comprising:
An iterative concatenated code decoding circuit, comprising an inner decoder for decoding the encoded data received through a transmission path and correcting the errors of said data, a deinterleaver for deinterleaving the data decoded by said inner decoder, an outer decoder for decoding the deinterleaved data and correcting the errors of said data, and an interleaver for interleaving the data decoded by said outer decoder, in which said inner decoder, said deinterleaver, said outer decoder and said interleaver are disposed at N (N is a positive integer) stages, said iterative concatenated code decoding circuit employing a concatenated code concatenating two codes of an outer code and an inner code, in which an coding ratio of each of said inner code and said outer code is represented by (code-word length−redundancy check length)/(code-word length),
An encoding/decoding system, comprising an encoding device for encoding a concatenated code concatenating two codes of an outer code and an inner code, and a decoding device including an iterative concatenated code decoding circuit for decoding said concatenated code, in which an coding ratio of each of said inner code and said outer code is represented by (code-word length−redundancy check length)/(code-word length),
An encoding/decoding system comprising an encoding device for encoding a concatenated code concatenating two codes of an outer code and an inner code, and an inner decoder for decoding the encoded data received through a transmission path from said encoding device and correcting the errors of said data, a deinterleaver for deinterleaving the decoded data, an outer decoder for decoding the deinterleaved data and correcting the errors of said data, and an interleaver for interleaving the data decoded by said outer decoder, in which said inner decoder, said deinterleaver, said outer decoder and said interleaver are disposed at N (N is a positive integer) stages, said iterative concatenated code decoding circuit employing the concatenated code concatenating two different outer code and inner code, in which an coding ratio of each of said inner code and said outer code is represented by (code-word length−redundancy check length)/(code-word length),
Dependencies are inferred from the claim text.