Distributed interface for parallel testing of multiple devices using a single tester channel
AssigneeFormFactor, Inc.
InventorsRichard S. Roy, Charles A. Miller
Life of this patent
Estimating the term…
Abstract
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.
Claims15
A system comprising:
- a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single device under test (DUT) on each set of tester I/O lines;
- and
- a contact assembly comprising a plurality of elements for contacting a plurality of signal locations of two or more DUTs, and circuitry having an input coupled to the at least one set of tester I/O lines and an output coupled to the probes, the circuitry providing said data values at the output and performing a comparison using data values read from the DUTs to determine errors, if any, in said DUTs, and providing error values indicative of said errors.
3a. The system of claim 2 wherein the circuitry provides an error bit on each of said I/O lines, each error bit representing the error status of a separate DUT.
3b. The system of claim 1 wherein each of the DUTs is part of a packaged semiconductor IC device being tested.
A contact assembly comprising:
- a plurality of probes for contacting a plurality of signal locations of two or more devices under test (DUTs);
- and
- first circuitry having an input coupled to a channel of a semiconductor tester, and an output coupled to the probes, the output driving data values into the DUTs in response to receiving said data values at the input, the circuitry sensing data values from the DUTs and providing error information in response to performing a comparison using data values.
An interface circuit for use when coupled between a tester of integrated circuits (ICs) and two or more devices under test (DUTs), comprising:
- an input for receiving test data and addresses from a channel of the tester;
- an output for writing said test data to the DUTs;
- and
- comparison circuitry providing error information in response to performing a comparison using data read from each of the DUTs to determine errors, if any, in said DUTs.
11a. The interface circuit of claim 10 wherein the compressed information indicates whether an error was determined in any one or more of said DUTs.
11b. The interface circuit of claim 11 wherein the compressed information does not indicate an exact bit location of said error.
An interface circuit for testing a plurality of DUTs, comprising:
- means for receiving a data value and an associated address as part of a test sequence;
- means for delivering a plurality of copies of said data value at a plurality of addresses each corresponding to said associated address;
- means for receiving a plurality of copies of read data values associated with said plurality of addresses;
- and
- means for performing comparisons using said plurality of copies of read data values to generate error values representing differences, if any, between said plurality of copies of read data values and said data value.
A method for testing a plurality of DUTs, comprising:
- receiving a data value and an associated address as part of a test sequence;
- delivering a plurality of copies of said data value at a plurality of addresses each corresponding to said associated address;
- receiving a plurality of copies of read data values associated with said plurality of addresses;
- and
- performing comparisons using said plurality of copies of read data values to generate error values representing differences, if any, between said plurality of copies of read data values and said data value.
Dependencies are inferred from the claim text.