Deterministic hardware reset for FRC machine
AssigneeIntel Corporation
InventorsSteven J. Tu, Hang T. Nguyen
Life of this patent
Estimating the term…
Abstract
A processor includes one or more execution cores, each execution core having an associated scan chain to provide data to a set of voltage nodes of the core. A reset module drives a data pattern onto the scan line, responsive to a reset event. The data pattern places the set of voltage nodes of each execution core into specified logic states. For a processor including multiple execution cores configured to operate in an FRC mode, identical data patterns are driven onto the scan chains to reduce indeterminacy in the reset machine state of the processor.
Claims30
An apparatus comprising:
- an execution core;
- a scan chain to transfer data to one or more nodes of the execution core;
- and
- a reset module to provide a bit pattern to the scan chain, responsive to a reset signal.
A method for resetting a processor comprising:
- detecting a reset event;
- applying a bit pattern to a scan chain of the processor, the bit patter to drive specified states to one or more processor nodes accessible through the scan chain.
A system comprising:
- first and second execution cores to be operated in an FRC mode, responsive to a mode bit, each of the execution cores including a scan chain to transfer data to a first set of nodes of the execution core;
- an FRC checker to be activated in FRC mode to compare data from the first and second execution cores;
- and
- a reset module to apply a bit pattern to the scan chains of the first and second execution cores, responsive to a reset event in the system.
An apparatus comprising:
- an execution core including a set of voltage nodes coupled through data and clock lines;
- a reset module to drive a data signal and a clock signal to the set of voltage nodes, responsive to occurrence of a reset event, the data signal to place the voltage nodes of the set in specified logic states.
Dependencies are inferred from the claim text.