Time shift circuit for functional and AC parametric test

A time shift circuit for a semiconductor test system for changing a delay timing of a portion of a test pattern for testing a semiconductor device, comprising:

• a counter for transferring delay value data in a normal mode and incrementing the delay value data in an AC parametric measurement mode to determine a delay timing of a portion of the test pattern applied to a device under test where a mode selection signal selects either the normal mode or the AC parametric measurement mode;
• a vernier delay unit for producing timing vernier data based on programmed delay data prepared in the semiconductor test system and the delay value data received from the counter;
• a timing generator for generating a timing edge for the specific portion of the test pattern based on the timing vernier data from the vernier delay unit;
• means for stroking an output signal of the device under test at the timing edge from the timing generator;
• and
• a strobe recovery circuit for determining pass or fail status of the output signal of the device under test and producing a fail signal when the output signal fails;
• wherein the fail signal is provided to the counter during the AC parametric measurement mode to increment the delay value data, thereby continuously shifting the timing edge for stroking the output signal of the device under test until a change of state in the output signal is detected.