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US 2003/0126529 A1Published application
Wafer burn-in test mode circuit
AssigneeHynix Semiconductor Inc.
InventorYong Deok Cho
Life of this patent
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Abstract
A wafer burn-in test mode circuit is described. In a wafer burn-in test mode, an output at respective stages may be decoded using a single address signal in a shift register to minimize the number of an address necessary to decode a test item. Therefore, the limit of a burn-in apparatus having a small number of a channel may be overcome. Various test items may be supported with only a single address signal.
Claims14
A wafer burn-in test mode circuit comprising:
- a command decoder configured to create a plurality of command signals in response to input signals for driving a semiconductor memory device;
- an address latch circuit configured to latch a plurality of address signals;
- a register configured to store a wafer burn-in address signal for a wafer burn-in test from the address latch according to a command signal from the command decoder;
- a wafer burn-in test mode entry circuit configured to generate a wafer burn-in test mode entry signal for performing the wafer burn-in test according to the wafer burn-in address signal and a command signal from the command decoder;
- a plurality of shift registers configured to shift the wafer burn-in address signal inputted from the register according to the wafer burn-in test mode entry signal and a wafer burn-in clock signal;
- a wafer burn-in test priority decision circuit configured to output test priority signals according to output signals of the shift registers;
- and
- a decoder configured to decode the output signals of the shift registers according to the priority signals and configured to output wafer burn-in test signals corresponding to a wafer burn-in test item.
5 more elements
Dependencies are inferred from the claim text.