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AssigneeMicron Technology, Inc.
InventorsRobert L. Totorica, Charles K. Snodgrass
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A system allowing testing a plurality of integrated circuits mounted on a common substrate is described. The testing system includes a failure processor mounted on the substrate. The substrate has a first signal port adapted to be coupled to a testing device. The failure processor has a second signal port coupled to the first signal port and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested. Each of the test ports may be coupled to a respective one of the integrated circuits. The failure processor is constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits. The failure processor is further constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port. As a result, many integrated circuits under test may share the first signal port through the failure processor, because the integrated circuits under test are not providing output data on the first signal port to an external test data evaluation apparatus. The efficiency with which integrated circuits may be tested is thereby increased.
A system for testing a plurality of integrated circuits mounted on a common substrate, the substrate having a first signal port adapted to be coupled to a testing device, the testing system comprising one or more failure processors mounted on the substrate,. each failure processor having a second signal port coupled to the first signal port, and a plurality of test ports corresponding in number to the number of integrated circuits mounted on the substrate that are to be tested by that failure processor, each of the test ports being coupled to a respective one of the integrated circuits, each failure processor being constructed to apply stimulus signals to each of the integrated circuits and to record response signals generated by each of the integrated circuits in response to the stimulus signals provided to the integrated circuits, each failure processor further being constructed to provide report data based on the response signals and to couple the report data from the second signal port to the first signal port.
A failure processor for testing a plurality of integrated circuits mounted on a common substrate along with the failure processor, the failure processor having a signal port adapted to be coupled to a testing device, the failure processor being coupled to each of integrated circuits mounted on the substrate that are to be tested, the failure processor comprising:
A testing system for testing a plurality of integrated circuits mounted on a common substrate, the testing system comprising:
A method of testing a plurality of integrated circuits mounted on a common substrate, the substrate having a signal port adapted to be coupled to a testing device, the method comprising:
Dependencies are inferred from the claim text.