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US 2003/0126525 A1Published application
Semiconductor device, method of testing the same and electronic instrument
AssigneeSeiko Epson Corporation
InventorsKoji Miyashita, Masaya Uehara
Life of this patent
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Abstract
A semiconductor device having a plurality of memory cells for storing data, an address input circuit having an address signal generation section for independently generating an address signal using a clock signal in a test mode, and a delay circuit for delaying an input time of the address signal from the address input circuit to a subsequent circuit for a predetermined time period which is equal to or longer than the time necessary for the generation of the address signal.
Claims13
A semiconductor device comprising:
- a plurality of memory cells for storing data;
- a clock signal input terminal to which a clock signal is inputted;
- a test mode signal input terminal to which a test mode signal for instructing operation in a test mode is inputted;
- an address generation section which generates an address signal for selecting part of the memory cells;
- and
- a delay circuit which delays an input time of the address signal from the address generation section to a subsequent circuit for a predetermined time period, based on the clock signal,
- wherein the address generation section has an address signal generation section which generates each bit of the address signal having a plurality of bits, using the clock signal in the test mode;
- and
- a plurality of address holding circuits which temporarily holds respective bit of the address signal.
6 more elements
A method of testing a semiconductor device comprising the steps of:
- generating an address signal having a plurality of bits by using a clock signal;
- and
- outputting the address signal to a subsequent circuit at a time delayed for a predetermined time period, based on the clock signal.
Dependencies are inferred from the claim text.