Automatic testing for multi-core architecture
AssigneeIntel Corporation
InventorAyman G. Abdo
Life of this patent
Estimating the term…
Abstract
A test circuit disposed between a common bus and the cores of a multi-core computer permits post-silicon validation in the form of controlled stress testing of the system. The test circuit may block data requests from one or more selected cores and issue test data requests into the system instead, resulting in a more controllable test environment. In one embodiment, the test circuit is programmed and monitored from an external device through an integrated test port.
Claims25
An apparatus, comprising:
- a test controller, coupled between a bus and first and second cores in a multi-core computer, to operate a data flow stress test in the multi-core computer.
A system comprising:
- a memory;
- a multi-core computer coupled to the memory;
- and
- a test controller, coupled between a bus and first and second cores in the multi-core computer, to operate a data flow stress test in the multi-core computer.
A method comprising:
- stress testing a multi-core computer by blocking a first data request from a first core to a bus and sending a test data request from a test controller to the bus.
A machine-readable medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:
- stress testing a multi-core computer by blocking a first data request from a first core to a bus and sending a test data request from a test controller to the bus.
A machine-readable medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:
- obtaining test data for stress testing a multi-core computer system;
- writing the test data to a test register in the multi-core computer system through a test port;
- and
- reading a test result from the test register through the test port.
Dependencies are inferred from the claim text.