Secure EEPROM memory comprising an error correction circuit
AssigneeSTMicroelectronics S.r.l.
InventorSylvie Wuidart
Life of this patent
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Abstract
An electrically erasable and programmable memory includes at least one non-erasable secured zone. Detection and/or correction of read errors in the secured zone is provided by recording redundant bits in the secured zone and delivering an error signal and/or a bit having the majority value when the redundant bits read in the secured zone are not equal.
Claims49
An electrically erasable and programmable memory comprising:
- a memory array comprising erasable and programmable zones and at least one non-erasable secured zone;
- and
- means for detecting and correcting read errors in said at least one non-erasable secured zone by recording a plurality of redundant bits corresponding to each programmed bit being recorded therein and generating at least one of an error signal and a bit having a majority value when the corresponding plurality of redundant bits read are not the same.
An electrically erasable and programmable memory comprising:
- a memory array comprising erasable and programmable zones and at least one non-erasable secured zone;
- and
- means for detecting read errors in said at least one non-erasable secured zone by recording a plurality of redundant bits corresponding to each programmed bit being recorded therein and generating an error signal when the corresponding plurality of redundant bits read are not the same.
An integrated circuit comprising:
- a microprocessor;
- a memory connected to said microprocessor and comprising
- a memory array comprising erasable and programmable zones and at least one non-erasable secured zone;
- and
- a first error detection circuit and a first error correction circuit for detecting and correcting read errors in said at least one non-erasable secured zone by recording a plurality of redundant bits corresponding to each programmed bit being recorded therein and delivering at least one of an error signal and a bit having a majority value when the corresponding plurality of redundant bits read are not the same.
An integrated circuit comprising:
- a microprocessor;
- a memory connected to said microprocessor and comprising
- a memory array comprising erasable and programmable zones and at least one non-erasable secured zone;
- and
- a first error detection circuit for detecting read errors in said at least one non-erasable secured zone by recording a plurality of redundant bits corresponding to each programmed bit being recorded therein and delivering an error signal when the corresponding plurality of redundant bits read are not the same.
A method for detecting and correcting read errors in an electrically erasable and programmable memory comprising a memory array having erasable and programmable zones and at least one non-erasable secured zone, the method comprising:
- recording a plurality of redundant bits in the at least one non-erasable secured zone corresponding to each programmed bit being recorded therein;
- and
- reading the plurality of redundant bits corresponding to the programmed bit and generating at least one of an error signal and a bit having a majority value when the plurality of redundant bits read are not the same.
A method for detecting read errors in an electrically erasable and programmable memory comprising a memory array having erasable and programmable zones and at least one non-erasable secured zone, the method comprising:
- recording a plurality of redundant bits in the at least one non-erasable secured zone corresponding to each programmed bit being recorded therein;
- and
- reading the plurality of redundant bits corresponding to the programmed bit and generating an error signal when the plurality of redundant bits read are not the same.
Dependencies are inferred from the claim text.