Method and apparatus for efficiently implementing trace and/or logic analysis mechanisms on a processor chip
AssigneeHewlett-Packard Development Company, L.P.
InventorTimothe Litt
Life of this patent
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Abstract
A system is disclosed in which an on-chip logic analyzer (OCLA) is included in an integrated circuit, such as a microprocessor. During debug modes, one or more sets of an on-chip cache memory are disabled from use by other circuitry in the integrated circuit, and reserved exclusively for use by the OCLA. Data stored in the reserved cache set can then be read out by the OCLA, and placed in a register that can be accessed by other logic internal or external to the integrated circuit. If the integrated circuit is operating under normal mode, the cache memory set can be used in conventional fashion by other circuitry with in the integrated circuit to enhance performance.
Claims29
An integrated circuit fabricated on a chip, comprising:
- an on-chip logic analyzer;
- a cache memory that includes a plurality of cache sets;
- at least one on-chip logic device that stores data to said plurality of cache sets during normal operation;
- and
- a logic gate that receives an enable signal when the on-chip logic analyzer is enabled, and which disables at least one of said plurality of said cache sets for storing data from said on-chip logic analyzer.
A processor, comprising:
- a CPU core;
- a cache memory coupled to said CPU core, said cache memory including a plurality of cache sets that during normal operation store data written by the CPU core;
- and
- at least one logic analyzer that receives information relating to the internal state of the processor, said logic analyzer being coupled to at least one of said plurality of cache sets, and wherein said logic analyzer is capable of gaining ownership of said at least one cache set to store selected portions of said received information when said on-chip logic analyzer is enabled.
A processor fabricated on a chip, comprising:
- a cache memory divided into a plurality of cache sets;
- test logic coupled to said cache memory, which tests the cache sets during system initialization and determines which cache sets are operative;
- a cache controller that controls the storage and retrieval of data from said cache memory, with said cache controller only storing data to cache sets that are determined to be operative by the test logic;
- a CPU core coupled to said cache memory, said CPU core storing data to all operative cache sets during normal operation;
- an on-chip logic analyzer capable of receiving data reflecting the internal state of the processor, said on-chip logic analyzer coupled to at least one cache set, which is disabled from use by the CPU core when the on-chip logic analyzer is enabled.
A method of maintaining state data of a processor in a cache memory set, comprising the acts of:
- enabling an on-chip logic analyzer to receive and select data for storage;
- disabling a cache set from use by any device other than the on-chip analyzer;
- storing said selected data in the disabled cache set.
Dependencies are inferred from the claim text.