Method and apparatus for clock and power control in wireless systems

In a baseband processor for wireless applications a method comprising:

• receiving a first indicator signal from a first module requiring a first clock signal derived from a system oscillator, the first indicator signal having a first state which indicates that the first clock signal is required and a second state which indicates that the first clock signal is not required;
• receiving a second indicator signal from a second module requiring a second clock signal derived from the system oscillator, the second indicator signal having a first state which indicates that the second clock signal is required and a second state which indicates that the second clock signal is not required;
• disabling the system oscillator when the first indicator signal is the second state and the second indicator signal is in the second state;
• and
• enabling the system oscillator when system oscillator output is required by at least one of the group comprising the first module and the second module.

A baseband processor for wireless applications, comprising:

• a first module requiring a first clock signal derived from a system oscillator, the first module providing a first indicator signal having a first state which indicates that the first clock signal is required and a second state which indicates that the first clock signal is not required;
• a second module requiring a second clock signal derived from the system oscillator, the second module providing a second indicator signal having a first state which indicates that the second clock signal is required and a second state which indicates that the second clock signal is not required;
• and
• a power management circuit for blocking passage of the first clock signal to the first module when the first indicator signal is in the second state and blocking passage of the second clock signal to the second module when the second indicator signal is in the second state and allowing passage of the first clock signal when the first indicator is in the first state and allowing passage of the second clock signal when the second indicator is in the first state.

In a baseband processor for wireless applications, a method comprising:

• receiving a first indicator signal from a first module requiring a first clock signal derived from a system oscillator, the first indicator signal having a first state which indicates that the first clock signal is required and a second state which indicates that the first clock signal is not required;
• receiving a second indicator signal from a second module requiring a second clock signal derived from the system oscillator, the second indicator signal having a first state which indicates that the second clock signal is required and a second state which indicates that the second clock signal is not required;
• and
• blocking passage of the first clock signal to the first module when the first indicator signal is in the second state and blocking passage of the second clock signal to the second module when the second indicator signal is in the second state and allowing passage of the first clock signal to the first module when the first indicator signal is in the first state and allowing passage of the second clock signal to the second module when the first indicator signal is in the first state.

In a baseband processor for wireless applications, a method comprising:

• receiving a first indicator signal from a first module requiring a first clock signal derived from a system oscillator, the first indicator signal having a first state which indicates that the first clock signal is required and a second state which indicates that the first clock signal is not required;
• disabling the system oscillator when the first indicator signal is the second state;
• and
• enabling the system oscillator when the system oscillator is required by the first module.