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US 2003/0126485 A1Published application
Power reduction in a memory bus interface
AssigneeIntel Corporation
InventorsJeffrey R. Wilcox, Noam Yosef
Life of this patent
Estimating the term…
Abstract
A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.
Claims30
A method comprising:
- amplifying data signals from a memory bus;
- sampling the amplified data signals;
- and
- selectively disabling the amplification in response to the absence of a predetermined operation occurring over the memory bus.
1 more element
A method comprising:
- amplifying data signals from a memory bus;
- sampling the amplified data signals;
- and
- selectively enabling the amplification in response to a predetermined operation occurring over the memory bus.
1 more element
An apparatus comprising:
- amplifiers to amplify data signals received from a memory bus;
- a first circuit coupled to the amplifiers to sample the amplified data signals;
- and
- a second circuit to selectively disable the amplifiers in response to the absence of a predetermined operation occurring over the memory bus.
1 more element
An apparatus comprising:
- amplifiers to amplify data signals received from a memory bus;
- a first circuit coupled to the amplifiers to sample the amplified data signals;
- and
- a second circuit to selectively enable the amplifiers in response to the predetermined operation occurring over the memory bus.
1 more element
A computer system comprising:
- a memory;
- a memory bus coupled to the memory;
- a processor to initiate a predetermined operation with the memory over the memory bus;
- amplifiers to amplify data signals received from the memory bus;
- a first circuit coupled to the amplifiers to sample the amplified data signals;
- and
- a second circuit to selectively disable the amplifiers in response to the absence of the predetermined operation occurring over the memory bus.
4 more elements
A computer system comprising:
- a memory;
- a memory bus coupled to the memory;
- a processor to initiate a predefined operation with the memory over the memory bus;
- amplifiers to amplify data signals received from the memory bus;
- a first circuit coupled to the amplifiers to sample the amplified data signals;
- and
- a second circuit to selectively enable the amplifiers in response to the predetermined operation occurring over the memory bus.
4 more elements
Dependencies are inferred from the claim text.