Reduced power option
AssigneeMicrochip Technology Incorporated
InventorMichael I. Catherwood
Life of this patent
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Abstract
A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one processor cycle and with one power mode instruction employing clock transition logic within the processor to initiate a switch to the clock source configuration specified by a literal, such as a 3-bit literal. Operand may be written the register of clock transition logic to define an exit state for a sleep mode.
Claims33
A method of processing power mode instruction, comprising:
- fetching and decoding a power mode instruction;
- and
- executing the power mode instruction on a combination of a CPU clock source and a peripheral clock source, wherein the power mode instruction initiates a switch to a clock source configuration associated with a literal
A processor for performing a power mode instruction, comprising:
- a program memory for storing instructions including a shadow register array control instruction;
- a program counter for identifying current instructions for processing;
- and
- a clock transition logic for executing the power mode instruction on a combination of a CPU clock source and a peripheral clock source, wherein the power mode instruction initiates a switch to a clock source configuration associated with a literal
Dependencies are inferred from the claim text.