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US 2003/0126478 A1Published application
Multiple mode power throttle mechanism
AssigneeIntel Corporation
InventorsJames S. Burns, Stefan Rusu, David J. Ayers, Edward T. Grochowski, Marsha Eng, Vivek Tiwari
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Abstract
A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline, and to determine a power state for the processor from the monitored activity. One of two or more power control mechanisms is engaged, responsive to the power state of the processor reaching a threshold.
Claims19
A system comprising:
- an execution pipeline;
- a digital throttle to estimate a power state, responsive to activity of the execution pipeline, and to trigger one of a plurality of power-control mechanisms, responsive to the estimated power state reaching a first threshold.
A method comprising:
- monitoring an activity level of a processor to determine a power state;
- activating a first power control mechanism if the power state meets a first threshold;
- and
- monitoring a status associated with the first power control mechanism;
- and
- activating a second power control mechanism responsive to the monitored status.
3 more elements
An apparatus comprising:
- an execution pipeline including one or more units to execute instructions;
- an activity monitor to estimate an activity level for the processor, responsive to a activity states of the one or more units;
- a throttle circuit to trigger a first power mode, responsive to a power state determined from the estimated activity level reaching a first threshold;
- and
- a mode circuit to track a status associated with the first power mode and to trigger a second power mode, responsive to the status reaching a second threshold.
2 more elements
Dependencies are inferred from the claim text.