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US 2003/0126419 A1Published application
Exception masking in binary translation
AssigneeIntel Corporation
InventorsBaiming Gao, Yun Wang, Yigal Zemach, Orna Etzion, Jianhui Li
Life of this patent
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Abstract
Mapping of exception masks between source and target architectures with different numbers of exception masks enables a binary translator to translate code from the source to the target architecture and to determine an appropriate state for the source architecture if an exception is raised when executing the translated code.
Claims30
A method comprising:
- mapping a plurality of exception masks in a source architecture to an exception mask in a target architecture;
- executing translated code in the target architecture, the translated code representing binary code in the source architecture;
- and
- determining a state for the source architecture if an exception is raised while executing the translated code.
1 more element
A machine-readable medium providing instructions, which when executed by a processing unit, causes the processing unit to perform operations comprising:
- mapping a plurality of exception masks in a source architecture to an exception mask in a target architecture;
- executing translated code in the target architecture, the translated code representing binary code in the source architecture;
- and
- determining a state for the source architecture if an exception is raised while executing the translated code.
1 more element
An apparatus comprising:
- a processing unit coupled to a memory through a bus;
- and
- a binary translation process executed from the memory by the processing unit to cause the processing unit to map a plurality of exception masks in a source architecture to an exception mask associated with the processing unit, execute translated code representing binary code in the source architecture, and determine a state for the source architecture if an exception is raised while executing the translated code.
Dependencies are inferred from the claim text.