Trace cache bypassing
AssigneeIntel Corporation
InventorsJohn Alan Miller, Stephan J. Jourdan
Life of this patent
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Abstract
A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.
Claims28
A method of managing processor instructions, the method comprising:
- decoding a first instruction into a plurality of operations with a decoder;
- passing a first copy of the operations from the decoder to a build engine associated with a trace cache;
- and
- passing a second copy of the operations from the decoder directly to a back end allocation module, the operations bypassing the build engine and the allocation module being in a decoder reading state.
A method of managing processor instructions, the method comprising:
- determining at a decoder whether a resume condition is present based on an instruction;
- and
- switching a backend allocation module of a processor from a decoder reading state to a trace cache reading state when the resume condition is present.
A method of managing instructions in a computer processing architecture having a trace cache, the method comprising:
- detecting a trace cache miss;
- receiving a first instruction;
- decoding the first instruction into a plurality of operations with a decoder;
- passing a first copy of the operations from the decoder to a build engine associated with the trace cache;
- passing a second copy of the operations from the decoder directly to a back end allocation module, the operations bypassing the build engine and the allocation module being in a decoder reading state;
- receiving a second instruction;
- determining at the decoder whether a resume condition is present based on the second instruction;
- and
- switching the allocation module from the decoder reading state to a trace cache reading state when the resume condition is present.
A processor instruction management system comprising:
- a decoder to decode a first instruction into a plurality of operations;
- and
- a controller to pass a first copy of the operations from the decoder to a build engine associated with a trace cache, the controller to pass a second copy of the operations from the decoder directly to an allocation module, the operations bypassing the build engine and the allocation module being in a decoder reading state.
Dependencies are inferred from the claim text.