Method and system to identify slowable instructions

A method, comprising:

• recording a first clock cycle when an instruction that loads data into a register is to complete;
• recording a second clock cycle when the data is read from the register;
• and
• making the instruction as a slowable instruction when the second clock cycle is more than a predetermined time threshold from the first clock cycle.

A computer readable medium having stored thereon sequences of instructions which are executable by a system, and which, when executed by the system, cause the system to perform a method, comprising:

• recording a first clock cycle when an instruction is to complete loading data in a register;
• recording a second clock cycle when the data is read from the register;
• and
• making the instruction as a slowable instruction when the second clock cycle is more than a predetermined time threshold from the first clock cycle.

A system, comprising:

• a processor;
• a memory coupled with the processor;
• and
• a register file coupled with the memory and the processor, wherein each of a plurality of registers in the register file is associated with an instruction address of an instruction that loads data into the register.