System and method of reducing the number of copies from alias registers to real registers in the commitment of instructions

A processor system comprising:

• a reorder buffer comprising a plurality of entries associated respectively with a plurality of instructions;
• and
• an allocator to:
• allocate one of said reorder buffer entries for an incoming instruction, wherein said allocated reorder buffer entry includes an alias register associated with a prior instruction;
• determine whether said incoming instruction designates a real register;
• and
• modify said allocated reorder buffer entry to include said incoming instruction with said alias register associated with said prior instruction if it is determined that said incoming instruction does not designate said real register.

A method comprising:

• providing a reorder buffer comprising a plurality of entries associated respectively with a plurality of instructions;
• allocating one of said reorder buffer entries for an incoming instruction, wherein said allocated reorder buffer entry includes an alias register associated with a prior instruction;
• modifying said allocated reorder buffer entry to include said incoming instruction;
• executing said incoming instruction which generates an alias register value;
• and
• determining whether to copy said alias register to said real register after the execution of said incoming instruction.

A processor system comprising:

• a reorder buffer comprising a plurality of entries associated respectively with a plurality of instructions;
• an allocator to:
• allocate one of said reorder buffer entries for an incoming instruction, wherein said allocated reorder buffer entry includes an alias register associated with a prior instruction;
• and
• modify said allocated reorder buffer entry to include said incoming instruction;
• an execution unit to execute said incoming instruction which generates a real register value;
• and
• a retirement unit to determine whether to cause the copying of said alias register to said real register after the execution of said incoming instruction.

A method comprising:

• providing a reorder buffer comprising a plurality of entries associated respectively with a plurality of instructions;
• executing an instruction of said plurality of instructions which generates a register value for a real register, said register value being stored in an alias register identified in an entry of said reorder buffer associated with said instruction;
• and
• determining whether said register value should be copied from said alias register to said real register approximately at a time when said entry of said reorder buffer is needed for a second instruction that is younger in order than said instruction plus a predetermined time delay.

A processor system comprising:

• a reorder buffer comprising a plurality of entries associated respectively with a plurality of instructions;
• an execution unit to execute an instruction of said plurality of instructions which generates a register value for a real register, said register value being stored in an alias register identified in an entry of said reorder buffer associated with said instruction;
• and
• an allocator to determine whether said register value should be copied from said alias register to said real register approximately at a time when said entry of said reorder buffer is needed for a second instruction that is younger in order than said instruction plus a predetermined time delay.